• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.371-380
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• 2006

The performance characteristics of the cell averaging(CA), greatest of(GO), and smallest of(SO) constant false alarm rate(CFAR) processors in homogeneous environment are obtained and compared when receiving antenna diversity is employed in the pseudonoise code acquisition of direct-sequence code division multiple access (DS/CDMA) systems. From the simulation results, it is observed that the CA CFAR scheme has the best performance and the GO CFAR scheme has almost the same performance as the CA CFAR scheme in homogeneous environment. In Part 2 of this paper, the CA, GO, and SO CFAR processors for code acquisition in nonhomogeneous environment are addressed.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.26-34
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• 2004

A blind interference canceller in the presence of subchipspaced multipath channels for direct-sequence code division multiple access (DS-CDMA) down-link system is considered. This technique is based on combining the existing blind interference canceller with a technique that involves assigning subchip-tap spacing to the Rake receiver. The proposed receiver minimizes the receiver’s output energy subject to a constraint in order to mitigate the multiple access interference (MAI) along each multipath component, and then suboptimally combining all the multipath components. Moreover, it is able to mitigate the mismatch problem when subchip-spaced multipath components arrive at the blind interference canceller. It is known that optimal combining techniques perform a decorrelation operation before combining, which requires both knowledge and computational complexity. In the following, we have adopted a simpler but suboptimum approach in the combining of the suppressed signals at the output of our proposed receiver. Computer simulation results verify the effectiveness of the proposed receiver to handle subchip-spaced multipath components and still suppresses MAI significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.330-335
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• 2002

In the direct sequence code division multiple access system, the problem of multiple access interference due to multiple access is generated. A interference cancelling receiver is used to solve this problem. The conventional interference cancelling receiver is structure of successive interference canceller using antenna array. In this structure, the difference of between method I and method II depends on updating weight vector. In this paper, the adaptive blind CMA array interference cancelling receiver using cost function of constant modulus algorithms is proposed to update weight vector at conventional structure. The simulation compared the proposed interference cancelling receiver with two conventional interference cancelling receivers by signal to interference ratio and bit error rate curve under additive white Gaussian noise environment. The simulation results show that the proposed receiver has about the gain of SIR of 1.5[dB] more than method I which is conventional receiver at SIR curve, and about the gain of SIR of 0.5(dB) more than method II. In BER curve, the proposed IC receiver about the gain of SNR of 2[dB] more than method I and about the gain of SNR of 0.5[dB] more than method If, Thus, the proposed interference cancelling receiver has the higher performance than conventional interference cancelling receivers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.213-218
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• 2007

In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.