• Progress in Superconductivity and Cryogenics
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• v.25 no.4
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• pp.54-59
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• 2023

In this paper, we analyze experimental results by applying the PHILS model to a lab-scale superconducting current limiter system for its actual application in medium-voltage direct current (MVDC) systems. Superconducting current limiters exhibit effective current-limiting performance in circuit breaker operations, particularly in limiting large fault currents within a short period, addressing the challenges posed by the increasing use of renewable energy and the integration of DC medium-voltage distribution systems. The development of such superconducting current limiters faces various technical and cost disadvantages, especially when applying a medium-voltage 35kV level system, which is intended for future introduction. The proven lab-scale superconducting current limiter system and the PHILS model are combined and integrated into the actual system. Our plan involves analyzing the limiter's performance, assessing its impact on the system, and preparing for its application in future medium-voltage systems. Utilizing RTDS, a simulation was conducted by connecting actual scaled-down equipment and systems, with the analysis results presented.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• Journal of Sensor Science and Technology
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• v.33 no.5
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• pp.391-398
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• 2024

Accurate positioning is essential for unmanned underwater vehicle (UUV) operations, particularly for long-term survey missions. To reduce the inherent positioning errors from the inertial navigation systems of UUVs, or dead reckoning, underwater terrain observations from sonar sensors are typically exploited. Within the framework of pose-graph optimization, we can generate submaps of the seafloor and use them to add loop-closure constraints to the pose graph by determining the best match between the submaps. However, this approach results in error accumulation in long-term operations because the quality of local submaps depends on the dead reckoning. Hence, we can adopt external acoustic positioning systems, such as an ultrashort baseline (USBL), to add global constraints to the existing pose graph. We assume that the acoustic transponder is installed on a UUV and that the acoustic transceiver is equipped in an unmanned surface vehicle trailing the UUV to maintain an acoustic connection between the vehicles. We simulate the terrain and USBL measurements as well as evaluate the performance of the UUV's pose estimation via online pose-graph optimization.

• Korean Journal of Clinical Laboratory Science
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• v.53 no.2
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• pp.158-164
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• 2021

Hypertriglyceridemia is the main risk factor for atherosclerosis. It is reported that triglyceride (TG) induces macrophage cell death, and is involved in the formation of plaques and development of atherosclerosis. We previously reported that TG-induced cell death of macrophages is mediated via pannexin-1 activation, which increases the extracellular ATP and subsequent increase in potassium efflux, thereby activating the caspase-2/caspase-1/apoptotic caspases, including the caspase-8 pathway. Contrarily, some studies have reported that caspase-8 is an upstream molecule of caspase-1 and caspase-2 in several cellular processes. Therefore, this study was undertaken to investigate whether caspase-8 influences its upstream molecules in TG-stimulated macrophage cell death. We first confirmed that caspase-8 induces caspase-3 activation and poly ADP-ribose polymerase (PARP) cleavage in TG-treated macrophages. Next, we determined that the inhibition of caspase-8 results in reduced caspase-1 and -2 activity, which are upstream molecules of caspase-8 in TG-induced cell death of macrophages. We also found that ATP treatment restores the caspase-8 inhibitor-induced caspase-2 activity, thereby implying that caspase-8 affects the upstream molecules responsible for increasing the extracellular ATP levels in TG-induced macrophage cell death. Taken together, these findings indicate that caspase-8 potentiates the TG-induced macrophage cell death by activating its upstream molecules.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.26 no.1
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• pp.17-26
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• 2008

The 1st order level network of Korea was adjusted simultaneously in 1987. After that, the 1 st order level network of Korea was adjusted simultaneously by National Geographic Information Institute in 2006. The levelling data were acquired by digital level with invar staff from 2001 through 2006. The 1st order level network consists of 36 level lines. Among them, 34 level lines comprise 11 level loops. Among 36 level lines, 4 level lines have fore & back error larger than the regulations for the 1st order levelling of NGII, Korea. Also, the closing error of 3 loops of level network exceed the regulation for the 1st order levelling of NGII. The standard error of fore and back leveling between bench marks(${\eta}_1$) are distributed between 0.2 $mm/{\surd}km$ and 1.7 $mm/{\surd}km$. The standard error of loop closing(${\eta}_2$) is 2.0 $mm/{\surd}km$. This result means that the 1st order level network of Korea qualifies for the high precision leveling defined by International Geodetic Association in 1948. As the result of the 1st order level network adjustment, the reference standard error($\hat{{\sigma}_0}$) of the level network was 1.8 $mm/{\surd}km$, which is twice as good as that of the 1st adjustment of level networks in 1987.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.411-414
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• 2008

The study is about simulation of optical circuit for oneself performance evaluation of Fiber Optic Gyro(FOG) closed-loop controller board. The Fiber Optic Interferometer Simulator is used a digital signal processing for cosine response specificity output of fiber optic coil about input rate. Response specificity of the fiber optic coil is $Vo(t)=K3[1+\cos\{K1(Vm(t)-Vm(t-{\tau}))+K2\}]$. Also the Fiber Optic Interferometer Simulator is able to confirm a output value with K1, K2 and K3 input. The fiber Optic Interferometer Simulator is able to oneself performance evaluation without fiber optical circuit. Because, it is the very same cosine response specificity of real fiber optic coil about input rate.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.