• 전기학회논문지
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• 제68권2호
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• pp.262-268
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• 2019

Previous dynamic models of hysteresis motor use an extended induction machine equivalent circuit or somewhat different equivalent circuit with conventional one, which makes unsatisfiable results. In this paper, the hysteresis dynamic characteristics of the motor rotor are analyzed using the inverse Preisach model and the hysteresis motor equivalent circuit considering eddy current effect. The hysteresis loop for the rotor ring is analyzed under full-load voltage source static state. The calculated hysteresis loop is then approximated to an ellipse for simplicity of dynamic computation. The permeability and delay angle of the elliptic loop apply to the dynamic analysis model. As a result, it is possible to dynamically analyze the hysteresis motor according to the applied voltage and the rotor material. With this method, the motor speed, generated torque, load angle, rotor current as well as synchronous entry time, hunting effect can be calculated.

• 전기전자학회논문지
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• 제22권4호
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• pp.1158-1162
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• 2018

안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수 증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ~ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는 MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.

• Journal of Power Electronics
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• 제15권5호
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• pp.1286-1294
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• 2015

Capacitor current feedback active damping is extensively used in grid-connected converters with an LCL filter. However, systems tends to become unstable when the digital control delay is taken into account, especially in low switching frequencies. This paper discusses this issue by deriving a discrete model with a digital control delay and by presenting the stable region of an active damping loop from high to low switching frequencies. In order to overcome the disadvantage of capacitor current feedback active damping, this paper proposes a modified approach using grid current and converter current for feedback. This can expand the stable region and provide sufficient active damping whether in high or low switching frequencies. By applying the modified approach, the active damping loop can be simplified from fourth-order into second-order, and the design of the grid current loop can be simplified. The modified approach can work well when the grid impedance varies. Both the active damping performance and the dynamic performance of the current loop are verified by simulations and experimental results.

• 대한전기학회논문지:전력기술부문A
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• 제53권7호
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• pp.365-374
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• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• 한국광학회지
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• 제8권5호
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• pp.426-430
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• 1997

개회로 구성 광섬유 자이로스코프(FOG)를 위한 폐회로 신호처리의 가능성을 밝히기 위한 신호처리기를 제작하였다. 이 신호처리기는 종래의 위상추적 신호처리 방식을 전디지털로 구현한 것으로서 광검출기의 출력단에서 곧바로 디지털로 변환하여 신호처리함으로써 잡음에 강한 FOG용 신호처리기로 동작할 수 있다. 또 이 신호처리기는 위상편이량 $2\pi$ 범위에서 최대 36비트의 분해능력을 가져 가장 분해능이 높은 신호처리기가 될 가능성이 있으며, 크기가 $2\pi$ 이상인 위상편이량도 측정할 수 있다. 제작된 신호처리기를 전 광섬유 FOG에 적용한 결과 적분시간이 1초일 때 위상차 분해능은 $3\mu$rad(회전율 0.74deg/hr에 해당)로서 지구의 자전속도를 충분히 확인할 수 있는 정도였다.

• 한국통신학회논문지
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• 제23권9A호
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• pp.2197-2210
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• 1998

In the grand alliance (GA) HDTV receiver, a coherent detection is empolyed for coherent demodulation of vestigial side-band (VSB) signal by using frequency and phaselocked loop(FPLL) operating on the pilot carrier. Additional phase tracking loop (PTL) employed to track out phase noise that has not been removed by the FPLL in theGA system. In this paper, we propose an algorithm for phase detection which utilizes a weighting function. The simplest implementation of the proposed algorithm using te sign of the Q channel component can be tractable by imposing a phase detection gain to the loop gain. It is obserbed that the propsoed algorithm has a robust characteristic against the performance of the digital filters used for Q channel estimation. A second goal of this paper is to introduce a gain control algorithm for the PTL in order to provide an effective implementation of the proposed phase detection algorithm. And we design the PTL through the realization of the simplified digital filter for H/W reduction. The proposed algorithms and the designed PTL are evaluated by computer simulation. In spite of using the simplified H/W structure, simulation results show that the proposed algorithms outperform the coventional PTL algorithms in the phase detection and tracking performance.

• 한국통신학회논문지
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• 제26권11B호
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• pp.1565-1573
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• 2001

디지털 위성방송 수신용 QPSK복조기에서 반송파 위상 오차의 발생으로 인한 문제점을 해결하기 위해서 반송파 복원 회로가 요구된다. 기존 반송파 복원 회로의 NCO(Numerically Controlled Oscillator)는 Look-up table을 갖는 구조로 되어있어 전력 소모가 큰 단점을 가지고 있다. 따라서 본 논문에서는 전력소모를 줄이기 위해 Look-uptable을 사용하지 않는 조합 회로의 구조로 NCO를 설계하였다. 제안된 NCO의 소비 전력을 비교해보면 Look-uptable을 사용한 NCO의 경우 175(7)이고 새로운 구조의 NCO는 24.65(7)의 결과로 전력소모가 약 1/8로 감소됨을 확인하였다. 또한, 설계한 반송파 복원 회로를 사용하여 위상 오차를 보정해 줄 수 있다는 것을 모의실험을 통해 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.400-402
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• 1994

This paper presents a digital implementation of delta modulation Technique for Active Power Filters. Delta modulated scheme is to control the harmonic-compensating current indirectly by adjusting the capacitor voltage to be sinusoidal. The overall control system has two feedback loops. One is the outer propotional feedback for loop regulating the dc current of active filters and the other is the inner feedback loop for maintaining the ac current waveform to be sinusoidal, and have zero power factor angle(i.e. unity power factor). The characteristics of the proposed is investigated by digital simulation using ACSL and experimental results are obtained by TMS370C756 Single-Chip Microprocessor relative to analog delta modulation technique.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1529-1536
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• 2017

A digital dual-channel interleaved phase-shift full-bridge converter is investigated in this paper, and its topology and principle are analyzed. To realize current sharing and stabilize the output voltage, a controller with current sharing loop and closed voltage loop is employed. In addition, current sharing will increase the output current fluctuation and a new digital interleaved driving technology is proposed to reduce the output current ripple. To verify the analysis, simulation and experiments are carried out, which shows the effectiveness of the proposed control strategies.

• Journal of Power Electronics
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• 제12권4호
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• pp.595-603
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• 2012

This paper presents a full digital control strategy for parallel connected modular inverter systems. Each modular inverter is a high frequency (HF) AC link inverter which is composed of a HF inverter and a HF transformer followed by a cycloconverter. To achieve equal sharing of the load current and to suppress the circulating currents among the modules, a three-loop control strategy, consisting of a common output voltage regulation (OVR) loop, individual circulating current suppression (CCS) loops and individual inner current tracking (ICT) loops, is proposed. The ICT loops are implemented with predictive current control from which high precision current tracking can be obtained. The effectiveness of the proposed control strategy is verified by simulation and experimental results from parallel connected two full-bridge HF AC link inverter modules.