• Journal of Power Electronics
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• v.15 no.2
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• pp.411-418
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• 2015

In this paper, a new method for the online estimation of equivalent series resistances (ESR) of the DC-link capacitors in induction machine (IM) drive systems with a front-end diode rectifier is proposed, where the ESR estimation is conducted during the regenerative operating mode of the induction machine. In the first place, a regulated AC current component is injected into the q-axis current component of the induction machine, which induces the current and voltage ripple components in the DC-link. By processing these AC signals through digital filters, the ESR can be estimated by a recursive least squares (RLS) algorithm. To acquire the AC voltage across the ESR, the DC-link voltage needs to be measured at a double sampling frequency. In addition, the ESR current is simply reconstructed from the stator currents and switching states of the inverter. Experimental results have shown that the estimation error of the ESR is about 1.2%, which is quite acceptable for condition monitoring of the capacitor.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• Journal of electromagnetic engineering and science
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• v.1 no.2
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• pp.131-138
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• 2001

The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2271-2281
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• 1998

The wordlength optimization for the analog-to-digital converter in DS-CDMA receivers is very important for the efficient implementation of front-end digital demodulator blocks. Wideband CDMA systems reqire a very fast acquisition time, thus they prefer the matched filter base dreceiver architecture.However, the matched filter should san very long chips, and as a results, requires a large number of gates and a high-power consumption. In this paper, the quantization effects on the acquisition performance of the matched filter is analyzed stochastically. The quantization is modeled as a series of saturation and digitization procedures, because the distortion due to the saturation is signal dependent and causes very different effects when compared with that of the, random, digitization noise. Numerical results are obtained to show the optimum saturaton limit of the quantizer for a given wordlength. This analysis can give a guide to low-cost and low-powr digital implementations and assurance of the system performance without intensive simulations.

• ETRI Journal
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• v.29 no.5
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• pp.607-613
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• 2007

Most signal-to-noise ratio (SNR) estimation techniques in digital communication channels derive the SNR estimates solely from samples of the received signal after the matched filter. They are based on symbol SNR and assume perfect synchronization and intersymbol interference (ISI)-free symbols. In severe channel distortion where ISI is significant, the performance of these estimators badly deteriorates. We propose an SNR estimator which can operate on data samples collected at the front-end of a receiver or at the input to the decision device. This will relax the restrictions over channel distortions and help extend the application of SNR estimators beyond system monitoring. The proposed estimator uses the characteristics of the second order moments of the additive white Gaussian noise digital communication channel and a linear predictor based on the modified-covariance algorithm in estimating the SNR value. The performance of the proposed technique is investigated and compared with other in-service SNR estimators in digital communication channels. The simulated performance is also compared to the Cram$\acute{e}$r-Rao bound as derived at the input of the decision circuit.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.64-68
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• 2007

This paper describes the development of RF front.end equipment of a wide band high precision satellite navigation receiver to be able to receive the currently available GPS navigation signal and the GALILEO navigation signal to be developed in Europe in the near future. The wide band satellite navigation receiver with high precision performance is composed of L - band antenna, RF/IF converters for multi - band navigation signals, and high performance baseband processor. The L - band satellite navigation antenna is able to be received the signals in the range from 1.1 GHz to 1.6 GHz and from the navigation satellite positioned near the horizon. The navigation signal of GALILEO navigation satellite consists of L1, E5, and E6 band with signal bandwidth more than 20 MHz which is wider than GPS signal. Due to the wide band navigation signal, the IF frequency and signal processing speed should be increased. The RF/IF converter has been designed with the single stage downconversion structure, and the IF frequency of 140 MHz has been derived from considering the maximum signal bandwidth and the sampling frequency of 112 MHz to be used in ADC circuit. The final output of RF/IF converter is a digital IF signal which is generated from signal processing of the AD converter from the IF signal. The developed RF front - end has the C/N0 performance over 40dB - Hz for the - 130dBm input signal power and includes the automatic gain control circuits to provide the dynamic range over 40dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.379-388
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• 2007

This paper presents a real-time respiration and heartbeat detector comprised of a 1.6 GHz single-channel Doppler sensor and analog/digital signal processing block for remote vital sign detection. The RF front end of the Doppler sensor consists of an oscillator, mixer, low noise amplifier, branch-line hybrid and patch antenna. We apply artificial transmission lines(ATLs) to the branch-line hybrid, which leads to a size reduction of 40 % in the hybrid, while its performance is very comparable to that of a conventional hybrid. The analog signal conditioning block is implemented using second order Sallen-Key active filters and the digital signal processing block is realized with a LabVIEW program on a computer. The respiration and heartbeat detection is demonstrated at a distance of 50 cm using the developed system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.