• Journal of Digital Contents Society
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• v.10 no.1
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• pp.115-120
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• 2009

In traditional message ferrying schemes, only message ferries carry messages between partitioned networks. In this paper, we propose a new approach to make both finite-buffered c ferries and mobile nodes carry messages so that we reduce message delivery delay and increase throughput in delay tolerant networks. We evaluate our scheme against conventional message ferrying in terms of message delivery delay and throughput.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.68-76
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• 1994

In the automatic transistor sizing with computer for optimizing delay and the chip area of CMOS digital circuits, conventionally either a mathematical method or a heuristic method has been used. In this paper, we present a new method of transistor sizing, a sort of combination of the above two methods, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.151-160
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• 2009

While portable and wireless devices are pouring, a new network technology is needed as a breakthrough. The new network technology features large delays, intermittent connectivity, and absence of an end-to-end path from sources to destinations. A network which has one of those characteristics is called DTNs(Delay Tolerant Networks). The main 4 routing methods have been researched so far in extream environment. In this paper, we look into the reliability of DTMNs(Delay Tolerant Mobile Networks) in several different situations, and propose an algorithm that selects a positive routine by sending the only information of its position when making a connection to a detected node. We simulate the proposed algorithm here in DTN using ONE simulator. As a result, it shows that the algorithm reduces the number of message transmission each node.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.4
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• pp.1-6
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• 2011

In this paper, search-efficient Bi-directional-Chord(B-Chord) is proposed in P2P (peer-to-Peer) overlay network. Chord is the most popular P2P Look-up protocol. However, it applied to the mobile environment, the search success rate become lower and the request delay time increases. That is big problem. Thus, by improving the existing Chord, in this paper proposed B-Chord reduces the request delay time to in a mobile environment. Proposed B-Chord have the two Finger table and can search by selecting Finger table depending on the value of Key. By use these bi-directional, it can reduce the number of nodes Hop and search delay time. Thus, As a result, it will be able to increase the search success rate in a mobile environment.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.548-552
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• 2005

In most physical processes, the transfer function includes a time-delay, and in the general distributed control system using a computer network, an inherent time-delay exists due to the spatial separation between controllers and actuators. Under the circumstance where an input time-delay exits, the system response overshoots and tends to diverge. For this reasons described above, a controller design method is proposed for a discrete nonlinear system including input time-delay, which adopts the time-discretization using Taylor series. Controllers are synthesized using an input/output linearization method. Finally, several cases of the computer simulations were conducted, and the results validate the proposed methods.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.566-570
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• 2005

A digital controller for nonlinear time-delay system is proposed in this paper. A nonlinear time-delay system is discretized by using Taylor's discretization method. And the discretized system can be converted to a general nonlinear system. For this reason, general nonlinear controller synthesis can be applied to the discretized time-delay system. We adopted MAC controller synthesis for this study. Computer simulations are conducted to verify the performance of the proposed method. The results of simulation show good performance of the proposed controller synthesis and the proposed method is useful to control nonlinear time-delay system easily.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.807-810
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• 1998

This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.