• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.11
• /
• pp.1275-1284
• /
• 2010

100 MHz bandwidth and 1 Gbit/s data speed are needed in LTE-advanced for the next generation mobile communication system. Therefore, spectrum aggregation method has been studied recently to extend usable frequency bands. Also bandwidth utilization is increased since vacant frequencies are used to communicate. However, transceiver structure requires the digital RF and SDR. Therefore, frequency synthesizer and PA must operate over wide-bandwidth and RF impairments also increases in transceiver. Uplink of LTE advanced uses DFT-S OFDM using plural power amplifier. The effect of ICI increases in frequency domain of receiver due to phase noise and IQ imbalance. In this paper, we analyze influences of ICI in frequency domain of receiver considering phase noise and IQ imbalance in multiband system. Also, we separate phase noise and IQ imbalance effect from channel response in frequency domain of uplink system. And we propose a method to estimate the channel exactly and to compensate IQ imbalance and phase noise. Simulation result shows that the proposed method achieves the 2 dB performance gain of BER=$10^{-4}$.

• 전자공학회논문지 IE
• /
• v.47 no.4
• /
• pp.18-27
• /
• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.47-54
• /
• 2006

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference pre-amplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble-code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18um 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral non-linearities of the prototype ADC are within 1.0LSB and 1.3LSB, respectively. The dual-channel ADC has an active area of $4.0mm^2$ and consumes 594mW at 1GS/s and 1.8V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.30 no.6
• /
• pp.467-478
• /
• 2019

This paper describes the development and measurement results of a wide-band planar active phase array antenna system for an electronic warfare jamming transmitter. The system is designed as an $8{\times}8$ triangular lattice array using a $45^{\circ}$ slant wide-band antenna. The 64-element transmission channel is composed of a wide-band gallium nitride(GaN) solid state power amplifier and a gallium arsenide(GaAs) multi-function core chip(MFC). Each GaAs MFC includes a true-time delay circuit to avoid a wide-band beam squint, a digital attenuator, and a GaAs drive amplifier to electronically steer the transmitted beam over a ${\pm}45^{\circ}$ azimuth angle and ${\pm}25^{\circ}$ elevation angle scan. Measurement of the transmitted beam pattern is conducted using a near-field measurement facility. The EIRP of the designed system, which is 9.8 dB more than the target EIRP performance(P), and the ${\pm}45^{\circ}$ azimuth and ${\pm}25^{\circ}$ elevation beam steering fulfill the desired specifications.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
• /
• v.18 no.1
• /
• pp.24-30
• /
• 2006

Three liquid cooling heat exchangers for cooling of telecommunication equipment were designed and their cooling performances were tested. The liquid cooling heat exchangers had twelve rectangular channels $(5\times3 mm)$ with different flow paths of 1, 4, and 12. Silicon rubber heaters were used to provide heat flux to the test section. Heat input was varied from 75 to 400 W, while flow rate and inlet temperature of working fluid were altered from 1.2 to 4.0 liter/fin and from 15 to 3$30^{\circ}C$, respectively. The 4-path heat exchanger showed lower and more uniform average inner temperatures between heaters and the surface of heat exchanger than those of the others. To obtain optimal distribution of working fluid to each channels of liquid cooling heat exchangers, 2-3-2 and 4-3 type tube distributors were designed, and their distribution performances of working fluid were numerically and experimentally investigated. The distributor of the 2-3-2 type showed superior distribution performance compared with those of the 4-3 type distributor.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.6
• /
• pp.1231-1243
• /
• 1997

Digital satellite communication channels have nonlinearities with memory due to saturation characteristics of traveling wave tube amplifier in the satellite and transmitter/receiver linear filters. In this paper, we propose a network structure and a learning algorithm for complex pi-sigma network (CPSK) and exploit CPSN in the problem of equalization of nonlinear satellite channels. The proposed CPSN is a complex-valued extension of real-valued pi-sigma network that is a higher-order feedforward network with fast learning while greatly reducing network complexity by utilizing efficient form of polynomials for many input variables. The performance of the proposed CPSN is demonstrated by computer simulations on the equalization of complex-valued QPSK input symbols distorted by a nonlinear channel modeled as a Volterra series and additive noise. The results indicate that the CPSN shows good equalization performance, fast convergence, and less computations as compared to conventional higher-order models such as Volterra filters.

• Journal of Biomedical Engineering Research
• /
• v.28 no.3
• /
• pp.429-440
• /
• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.3
• /
• pp.46-55
• /
• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.55-64
• /
• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.12
• /
• pp.184-193
• /
• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.