• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1281-1292
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• 2014

Photovoltaic (PV) solar systems with series-connected module integrated converters (MICs) are receiving increased attention because of their ability to create high output voltage while performing local maximum power point tracking (MPPT) control for individual solar panels, which is a solution for partial shading effects in PV systems at panel level. To eliminate the partial shading effects in PV system more effectively, sub-MICs are utilized at the cell level or grouped cell level within a PV solar panel. This study presents the results of a series-output-connection MPPT (SOC-MPPT) controller for sub-MIC architecture using a single sensor at the output and a single digital MPPT controller (sub-MIC SOC-MPPT controller and architecture). The sub-MIC SOC-MPPT controller and architecture are investigated based on boost type sub-MICs. Experimental results under steady-state and transient conditions are presented to verify the performance of the controller and the effectiveness of the architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.7C
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• pp.540-547
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• 2008

In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.6-14
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• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2303-2307
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• 2006

The round off noise properties of wave digital filters have known and desirable properties in respect to their realization with short coefficient wordlengths. This paper presents the optimal implementation of wave digital filters by employing multiprocessor archtectures in the sense of input sampling rate, the number of processors, and input-output delay. The implementation will be specified by complete circuit diagrams including control signals, and can be applied to an existing silicon complier for VLSI layout generation.

• ETRI Journal
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• v.26 no.4
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• pp.367-370
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• 2004

A new transmission system is necessary for the Digital Multimedia Broadcasting (DMB) service in Korea. Therefore, in this paper, we propose a new architecture for the implementation of a DMB transmission system based on Eureka-147. We describe the design and implementation of the Ensemble remultiplexer, which is essential to the proposed system for remultiplexing ETI frames and MPEG-2 transport streams. The proposed system provides a solution with high flexibility and low cost for multimedia broadcasting service. The functions of this transmission system have been verified by using our DMB receiver and other related systems.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.864-867
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• 2002

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. in this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtains a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.29-38
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• 2014

EDMS systems have been a main alternative for enterprise content management (ECM), which provide valuable functions for the effective control and management of organization-level digital contents. However, it has not been effective frequently for the purpose of integrative control of overall contents in an organization. One of reasons for this problem is that individuals usually create and store files with their own personal computers and do not move them to the central storage and control device, EDMS. Many occasions show that this situation can cause undesirable results for better management of enterprise contents. This paper introduced an approach of virtual folder which can directly connect individual computers and EDMS storage device without users' inconvenience. Adding the capacity of restricting usage of individual computer, users unavoidably and conveniently store and retrieve digital contents using EDMS server system. Several modules and implementing architecture for the virtual folder system are shown and the results of utilizing the system are explained with a case of application.

• Journal of Smart Tourism
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• v.4 no.1
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• pp.19-29
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• 2024

The objective of this article is to create a model of integrated management from the framework modeling of a digital collaborative network supported by knowledge engineering to make heritage site in the Brazil more effective. It is an exploratory and qualitative research with thematic analysis as technique of data analysis from the collaborative network, digital platform, world heritage, and tourism themes. The snowballing approach was chosen, and the mapping and classification of relevant studies was developed with the use of the spreadsheet tool and the Mendeley® software. The results show that the collaborative network model oriented towards strategic objectives should be supported by a digital platform that provides a technological environment that adds functionalities and digital platform services with the integration of knowledge engineering techniques and tools, enabling the discovery and sharing of knowledge in the collaborative network.

• The KIPS Transactions:PartD
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• v.12D no.2 s.98
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• pp.303-308
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• 2005

Generally, the overloaded server problem and the rapidly increased network traffic problem are happened in a center concentrated multimedia digital content service. Recently, a study about the CDN which is a digital content transmission technology to solve these problems are performed actively. In this study, we proposed the SDCDS which improved a process latency time and a security performance on a digital content delivery and management. The goal of the SDCDS is the digital content security and the improvement of the processing time. For that, we have to design the security and the caching method considering the architecture characteristics of the CDN. In the SDCDS, the public key encryption method is designed by considering the architecture characteristics of CDN. And we improved the processing latency time by improved the caching method which uses the grouped caching method on the encrypted DC and the general DC. And in the experiment, we veryfy the performance of the proposed system.