• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.258-264
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• 2015

The first 77 GHz transceiver that applies a heterodyne structure-based linear frequency modulation-frequency shift keying (LFM-FSK) front-end module (FEM) is presented. An LFM-FSK waveform generator is proposed for the transceiver design to avoid ghost target detection in a multi-target environment. This FEM consists of three parts: a frequency synthesizer, a 77 GHz up/down converter, and a baseband block. The purpose of the FEM is to make an appropriate beat frequency, which will be the key to solving problems in the digital signal processor (DSP). This paper mainly focuses on the most challenging tasks, including generating and conveying the correct transmission waveform in the 77 GHz frequency band to the DSP. A synthesizer test confirmed that the developed module for the signal generator of the LFM-FSK can produce an adequate transmission signal. Additionally, a loop back test confirmed that the output frequency of this module works well. This development will contribute to future progress in integrating a radar module for multi-target detection. By using the LFM-FSK waveform method, this radar transceiver is expected to provide multi-target detection, in contrast to the existing method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.132-139
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• 2016

In the bandpass sampling(BPS), the sampling frequency for the analog-to-digital converter is lower than that of the signal to be sampled. Since the BPS operation results in the signal spectrum to be copied on the baseband, it is possible for the frequency down-converter to be conveniently omitted. The second-order BPS system is introduced in order to cancel the aliased interference components from the BPS output that may be generated by the BPS processing. In this paper, we introduce a design method for the optimal phase of the interpolant filter in the second-order BPS system which enables to maximally cancel the aliased components. Being mathematically derived, this method can always be applied independently to the spectral characteristics of the BPS input signal. The performance improvements by the suggested method has been measured statistically with various power spectra of the received signal, and it has been shown that the maximal amount of the improvements reaches up to 5~20 [dB] in comparison with the previous suboptimal algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.209-216
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• 2009

The repeater for wireless broadband internet (Wibro) system using OFDM demands the short processing delay to eliminate inter-symbol interference resulted from the time delay greater than the guard time. Towards this, the total system delay of repeater is expected to be minimized as possible as it can without distorting signal quality. In general, the FIR-type of filter is commonly deployed as a channelization filter, but due to its large amount of coefficients for producing prerequisite filter response the excessive large time delay occurs. To withstand this problem, the paper proposes the method for designing IIR filter whose response almost identical to that of the original filter. Moreover, in order to linearize the phase response of the designed IIR filter, this paper also introduce the way of designing the all-pass filter to be cascaded works for linearizing phase response of the channelization as well as the de-channelization filter. To achieve the further improvement in linearization of the phase response and reduction of the overall complexity, this paper tries to transform the integrated IIR filter group into the structure in polyphase style. The computer simulation verifies that the integrated IIR filter group designed in this paper reveals the relatively short processing delay without harming the acceptible signal quality.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1085-1097
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• 2009

We present a structure and design method of the D8PSK modem compatible with the VDL mode-2 standard and performance test results of the developed modem. In VDL mode-2, the raised cosine filter is used only in the transmitter and a general low pass filter is used in the receiver. Consequently, we can not achieve ISI reduction but can have better spectrum characteristics. Although there is 1~2 dB performance degradation with an un-matched filter compared to that with a matched filter, it is more important to minimize adjacent channel interference in narrow band communications. The transmit signal is generated digitally to avoid the problems(I/Q imbalance and DC offset etc.) of analog modulators. In addition the digital down converter using digital IF sampling technique is adopted for the receiver. This paper contains the overall configuration, design method and simulation results based in part on the previously proposed structures and algorithms. It is confirmed that the modem transmits and receives messages successfully at a speed of max. 870 km/h over ranges of up to 310 km through the ground and in-flight communication tests.