• Title/Summary/Keyword: Digital Information Display

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Efficiency Analysis of the Korean Listed Display Companies (국내 상장 디스플레이 기업의 효율성 분석)

  • Seo, Kwang-Kyu
    • Journal of Digital Convergence
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    • v.10 no.9
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    • pp.159-164
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    • 2012
  • Although the display industry plays an important role in the entire Korean economy, few empirical research has analyzed the efficiency of display companies. The purpose of this paper is to measure and analyze efficiency of korean listed display firms using DEA(Data Envelopment Analysis) models. We evaluate the CCR and BCC efficiency in DEA models and the return to scale of the Korean listed display companies. The benchmarking companies and efficiency value for the display companies with inefficiency are also provided to improve their efficiency. We analyzed the 44 listed companies consisted of 7 listed on KOSPI and 37 listed on KOSDAQ at the end of 2010. The analysis results show six companies whose values of CCR are 1, and fourteen firms whose values of BCC efficiency are 1. In additions, the six companies have the scalability efficiency. Eventually the efficiency analysis can provide the valuable information for inefficient companies to find benchmarking companies and to improve their efficiency.

Investigation of Top-Contact Organic Field Effect Transistors by the Treatment Using the VDP Process on Dielectric

  • Kim, Young-Kwan;Hyung, Gun-Woo;Park, Il-Houng;Seo, Ji-Hoon;Seo, Ji-Hyun;Kim, Woo-Young
    • Journal of the Korean Applied Science and Technology
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    • v.24 no.1
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    • pp.54-60
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    • 2007
  • 이 논문에서는 게이트 절연막 위에 vapor deposition polymerization(VDP)방법을 사용하여 성막한 유기 점착층을 진공 열증착하여 유기 박막 트랜지스터(OTFTs)소자를 제작할 수 있음을 증명하였다. 우리가 제작한 Staggered-inverted top-contact 구조를 사용한 유기 박막 트랜지스터는 전기적 output 특성이 포화 영역안에서는 포화곡선을, triode 영역에서는 비선형적인 subthreshold를 확실히 볼 수 있음을 발견했다. $0.2{\mu}m$ 두께를 가진 게이트 절연막위에 유기 점착층을 사용한 OTFTs의 장 효과 정공의 이동도와 문턱전압, 그리고 절멸비는 각각, 약 0.4cm2/Vs, -0.8V, 106 이 측정되었다. 게이트 절연막의 점착층으로써 폴리이미드의 성막을 위해, 스핀코팅 방법 대신 VDP 방법을 도입하였다. 폴리이미드 고분자막은 2,2bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride(6FDA)와 4,4'-oxydianiline(ODA)을 고진공에서 동시에 열 증착 시킨 후, 그리고 $150^{\circ}C$에서 1시간, 다시 $200^{\circ}C$에서 1시간 열처리하여 고분자화된 막을 형성하였다. 그리고 점착층이 OTFTs의 전기적 특성에 주는 영향을 설명하기 위해 비교 연구하였다.

CRT Development Strategy based on Customers' Safety and Requirements (소비자의 안전 및 제품에 대한 요구를 고려한 CRT의 개발방향)

  • 장성호;김상호
    • Journal of the Korea Safety Management & Science
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    • v.3 no.3
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    • pp.23-32
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    • 2001
  • In the era of digital technology, display device is the one of the important interface tool to communicate and transmit the information. Among the various display devices, CRT is the most popular one. Even though the CRT has many advantages comparing to other devices, it is faced to overcome its a few disadvantages especially in volume, shape and price, etc, In this paper, we try to show the development strategy of CRT corresponding with flat displays in the view point of ergonomics.

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Reducing the Poly-Si TFT Non-Uniformity by Transistor Slicing

  • Lee, Min-Ho;Lee, In-Hwan
    • Journal of Information Display
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    • v.2 no.2
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    • pp.27-31
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    • 2001
  • Transistor slicing refers to the use of multiple smaller transistors in implementing a large MOS transistor. What is special about transistor slicing is that it can reduce the effects of device non-uniformity introduced during the fabrication process. The paper presents the idea of transistor slicing and analyzes the benefits of using transistor slicing in the context of Poly-Si TFT-LCD driving.

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Computational Technique of Volumetric Object Reconstruction in Integral Imaging by Use of Real and Virtual Image Fields

  • Shin, Dong-Hak;Cho, Myung-Jin;Park, Kyu-Chil;Kim, Eun-Soo
    • ETRI Journal
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    • v.27 no.6
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    • pp.708-712
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    • 2005
  • We propose a computational reconstruction technique in large-depth integral imaging where the elemental images have information of three-dimensional objects through real and virtual image fields. In the proposed technique, we reconstruct full volume information from the elemental images through both real and virtual image fields. Here, we use uniform mappings of elemental images with the size of the lenslet regardless of the distance between the lenslet array and reconstruction image plane. To show the feasibility of the proposed reconstruction technique, we perform preliminary experiments and present experimental results.

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Particle Swarm Optimization based Haptic Localization of Plates with Electrostatic Vibration Actuators

  • Gwanghyun Jo;Tae-Heon Yang;Seong-Yoon Shin
    • Journal of information and communication convergence engineering
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    • v.22 no.2
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    • pp.127-132
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    • 2024
  • Haptic actuators for large display panels play an important role in bridging the gap between the digital and physical world by generating interactive feedback for users. However, the generation of meaningful haptic feedback is challenging for large display panels. There are dead zones with low haptic sensations when a small number of actuators are applied. In contrast, it is important to control the traveling wave generated by the actuators in the presence of multiple actuators. In this study, we propose a particle swarm optimization (PSO)-based algorithm for the haptic localization of plates with electrostatic vibration actuators. We modeled the transverse displacement of a plate under the effect of actuators by employing the Kirchhoff-Love plate theory. In addition, starting with twenty randomly generated particles containing the actuator parameters, we searched for the optimal actuator parameters using a stochastic process to yield localization. The capability of the proposed PSO algorithm is reported and the transverse displacement has a high magnitude only in the targeted region.

A Study on the Improvement of Tearing Artifact for Windows-Based Visual Monitoring Systems (윈도우즈 기반 영상 감시 시스템에서의 Tearing 현상 개선)

  • 정연권;이동학;정선태
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.11C
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    • pp.1097-1105
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    • 2002
  • In display systems employing analog monitors, the tearing artifact such that an window screen is divided into two parts showing different scenes can occur when the change of scenes in the moving pictures is very fast, but the frame buffer's refresh rate does not match the monitor's scanning frequency. It is especially noticeable at high frame rate. DVR system is a recently popularized visual monitoring system. The tearing artifacts becomes more serious since the frame buffer's refresh rate is very high due to the requirement of multi channel display in the DVR. In this paper, we propose an improved display system for windows-based DVR systems which prevents the tearing artifacts without deterioration of display speed performance. The efficiency of the proposed display system is verified through experiments.

TheReviser : A Gesture-based Editing System on a Digital Desk (TheReviser : 가상 데스크 상의 제스처 기반 문서 교정 시스템)

  • Jung, Ki-Chul;Kang, Hyun
    • The KIPS Transactions:PartB
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    • v.11B no.4
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    • pp.527-536
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    • 2004
  • TheReviser is a digital document revision application on a projection display, which allows us to interact a digital document with the same gestures used for paper documents revision. To enable these interactions, TheReviser should detect foreground objects such as hands or pens on a projection display, and should spot and recognize gesture commands from continuous movements of a user. To detect foreground objects from a complex background in various lighting conditions, we perform geometry and color calibration between a captured image and a frame buffer image. TheReviser uses an HMM-based gesture recognition method Experimental results show that the proposed application recognizes user's gestures on average 93.22% in test gesture sequences.

Development of the Interface Module for an Effective Application of a Digital Mockup

  • Song, Tai-Gil;Kim, Sung-Hyun;Lim, Gwang-Mook;Yoon, Ji-Sup;Lee, Sang-Ho
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2407-2409
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    • 2005
  • As the cumulative amount of spent fuel increases, the reliable and effective management of the spent fuel has become a world-wide mission. For this mission, KAERI is developing the Advanced Spent Fuel Conditioning Process (ACP) as a pre-disposal treatment process for spent fuel. Conventional approach to the development of the process and the remote operation technology is to fabricate the process equipment on the same scale as the real environment and demonstrate the remote handling operation using simulated fuel called a mock-up test. But this mock-up test is expensive and time consuming, since the design may need to be modified and the equipment fabricated again to account for the problems found during a testing. To deal with this problem, we developed a digital mockup for the ACP. Also, for an effective utilization of the digital mockup, we developed user interface modules such as the data acquisition and display module and the external input device interface module. The result of this implementation shows that a continuous motion of the manipulator using the external device interface can be represented easily and the information display screens responded well to the simulation situation.

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Design of Low Area Decimation Filters Using CIC Filters (CIC 필터를 이용한 저면적 데시메이션 필터 설계)

  • Kim, Sunhee;Oh, Jaeil;Hong, Dae-ki
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.3
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    • pp.71-76
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    • 2021
  • Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.