• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.542-547
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• 2003

A new approach to design of a discrete-time robust $H_{\infty}$ filter in finite horizon case is proposed. It is shown that robust $H_{\infty}$ filtering problem can be cast into the minimization problem of an indefinite quadratic form, which can be solved by implementing the Kalman filter defined in Krein space. The proposed filter is readily derived by simply augmenting the state space model and has the robustness property against the parameter uncertainties of a given system.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.107-119
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• 1988

An 8-channel digital filter bank with wave digital filters(WDF) is studied. Wave digital filtwr is automatically a directional filter. Using these properties, a new method for organizing the 8-channel digital filter bank is proposed. This will lead to enormous savings in memories for the digital signal processign chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.12
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• pp.155-160
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• 2003

Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3087-3093
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• 2009

Digital filters are indispensible element in digital signal processing area. The performance of digital filter based on adding and multiplying operation, such as computational speed and power consuming is determined by the orders and coefficients of filter which has on effect area of semiconductor chip when it is implemented by VLSI technology. In this research, in order to performance improvement of digital filter, we proposed the algorithm to speed-up the operation of digital filter associated with the minimum signed digit representation of binary number system and method to simplify the digital filter design associated with common subexpression elimination. The performance of proposed method is evaluated by the computational speed and design-simplicity by experimental implemented digital filter on FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.973-976
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• 2009

Digital signal processing technique use to variety fields including communication. For these signal processing, FIR digital filter is representative. And for FIR digital filter designing, the window function is used to reduce the Gibbs phenomenon which occurs in the coefficient cutting process of the ideal filter. Therefore, in this paper to improve performance of digital filter, a high-order window function was applied. In this simulation, we compared a peak side-lobe and a transient characteristics with the existing window function.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.10
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• pp.630-638
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• 2005

In FIR (Finite Impulse Response) filter applications, Nth-band F]U digital filters are known to be important due to their reduced computational requirements. The conventional methods for designing F]U filters use iterative approaches such as the well-known Parks-Mcclellan algorithm. The Parks-Mcclellan algorithm is also used to design Nth-band FIR digital filters. But a disadvantage of the Parks-Mcclellan algorithm is that it needs a good amount of design time. This paper describes a direct design method for Nth-band FIR Filters using Chebyshev polynomials, which provides a reduced design time over indirect methods such as the Parks-Mcclellan algorithm. The response of the resulting filter is equiripple in passband. Our proposed method produces a passband response that is equripple to within a minuscule error, comparable to that of the Parks-Mcclellan algorithm.

• ETRI Journal
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• v.25 no.5
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• pp.345-355
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• 2003

In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.1
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• pp.37-42
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• 2009

The digital filter is essential element in digital signal processing area. It needs a high computational burden caused by multiplying and adding. The multiplier in digital filter is a dominant element, which occupies an wide area at the field of VLSI design, needs high power-consuming and also decides critical path that affects to filter performance. In this paper we proposed the simultaneous transform method which is represented 2's complementary representation to CSD and MSD representation to solve a complexity problem and to improve a computational speed. The performance of proposed method was implemented in VHDL and applied to an digital filters, was evaluated the decreasing of critical path delay.