• Journal of Advanced Navigation Technology
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• v.2 no.2
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• pp.116-125
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• 1998

Most of modern mobile communication systems require low distortion in addition to high power and high efficiency characteristics for power amplifiers. The power amplifiers cause adjacent channel interference by intermodulation and spectral regrowth. In order to analyze the effects of the power amplifier on communication system, a 22Mcps spreaded digital modulated signal source and a ISM band power amplifier have been constructed, ACPR characteristics are simulated and measured for the RZ and NRZ encoded signals.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.53-61
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• 2014

In this paper, we present the design, fabrication and measurement of high efficiency GaN HEMT power amplifier using harmonic matching technique. In order to achieve high efficiency, harmonic load-pull simulation is performed, that is, the optimum load impedances are determined at $2^{nd}$ and $3^{rd}$ harmonic frequencies as well as at the fundamental. Then, the output matching circuit is designed based on harmonic load-pull simulation. The measurement of the fabricated power amplifier shows the linear gain of 20 dB and $P_{1dB}$(1 dB gain compression point) of 33.7 dBm at 1.85 GHz. The maximum power added efficiency(PAE) of 80.9 % is achieved at the output power of 38.6 dBm, which belongs to best efficiency performance among the reported high efficiency power amplifiers. For W-CDMA input signal, the power amplifier shows a PAE of 27.8 % at the average output power of 28.4 dBm, where an ACLR (Adjacent Channel Leakage Ratio) is measured to be -38.8 dBc. Digital predistortion using polynomial fitting was implemented to linearize the power amplifiers, which allowed about 6.2 dB improvement of an ACLR performance.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.16-26
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• 2011

This paper presents high power and high efficiency Doherty amplifiers for 2.345 GHz wireless broadband (WiBro) applications that use a Nitronex 125-W ($P_{3dB}$) GaN high electron mobility transistor (HEMT). Two- and three-way Doherty amplifiers and a saturated Doherty amplifier using Class-F circuitry are implemented. The measured result for a center frequency of 2.345 GHz shows that the two-way Doherty amplifier attains a high $P_{3dB}$ of 51.5 dBm, a gain of 12.5 dB, and a power-added efficiency (PAE) improvement of about 16 % compared to a single class AB amplifier at 6-dB back-off power region from $P_{3dB}$. For a WiBro OFDMA signal, the Doherty amplifier provides an adjacent channel leakage ratio (ACLR) at 4.77 MHz offset that is -33 dBc at an output power of 42 dBm, which is a 9.5 dB back-off power region from $P_{3dB}$. By employing a digital pre-distortion (DPD) technique, the ACLR of the Doherty amplifier is improved from -33 dBc to -48 dBc. The measured result for the same frequency shows that the three-way Doherty amplifier, which has a $P_{3dB}$ of 53.16 dBm and a gain of 10.3 dB, and the saturated Doherty amplifier, which has a $P_{3dB}$ of 51.1 dBm and a gain of 10.3 dB, provide a PAE improvement of 11 % at the 9-dB back-off power region and 7.5 % at the 6-dB back-off region, respectively, compared to the two-way Doherty amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1102-1109
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• 2001

This paper presents the new architecture of an adaptive predistortion linearizer using the polynomial type predistorter. In the proposed linearizer, most of the processes, including the predistortion, are performed with a digital signal processor(DSP). The recursive least squares(RLS) algorithm is employed for the optimization process to minimize the errors between the predistorter and postdistorter output signals. Simulation results demonstrate that the adjacent channel power ratio(ACPR) is improved by greater than 40 dB at the band edge with linearization. The convergence and reconvergence performance of the linearizer is also satisfactory.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.9
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• pp.2456-2469
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• 1996

A digital satellite communication channel has a nonlinearity with memory due to saturation characeristis of the high poer amplifier in the satellite and transmitter/receiver linear filter used in the overall system. In this paper, we propose a complex radial basis function network(CRBFN) based adaptive equalizer for compensation of nonlinearities in digital satellite communication channels. The proposed CRBFN untilizes a complex-valued hybrid learning algorithm of k-means clustering and LMS(least mean sequare) algorithm that is an extension of Moody Darken's algorithm for real-valued data. We evaluate performance of CRBFN in terms of symbol error rates and mean squared errors nder various noise conditions for 4-PSK(phase shift keying) digital modulation schemes and compare with those of comples pth order inverse adaptive Volterra filter. The computer simulation results show that the proposed CRBFN ehibits good equalization, low computational complexity and fast learning capabilities.

• Journal of the Semiconductor & Display Technology
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• v.15 no.2
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• pp.55-60
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• 2016

This study was developed through the secondary battery module charging/discharger possible utilization in the production process equipment circuit. The developed module is ensuring construction of efficient and productive charging and discharger through this research a limit on the yield and the price of existing single -channel charge and discharger circuit as a 5V 70A grade secondary battery Formation charge and discharger for up to 1 board 4 channels. In order to improve the sensing accuracy, through a robust differential amplifier circuit described using 16bit Analog-Digital Converter and noise was secured 16bit resolution sensing. The configuration also made demands for property Rise / Fall Time. Data Acquisition, discharge efficiency and also to fit the sink circuit temperature level for mass production.

• Journal of Astronomy and Space Sciences
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• v.27 no.3
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• pp.221-230
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• 2010

A 4+12+16 amplitude phase shift keying (APSK) modulation outperforms other 32-APSK modulations in a nonlinear additive white Gaussian noise (AWGN) channel because of its intrinsic robustness against AM/AM and AM/PM distortions caused by the nonlinear characteristics of a high-power amplifier. Thus, this modulation scheme has been adopted in the digital video broadcasting-satellite2 European standard. And it has been considered for high rate transmission of telemetry data on deep space communications in consultative committee for space data systems which provides a forum for discussion of common problems in the development and operation of space data systems. In this paper, we present an improved bits-to-symbol mapping scheme with a better bit error rate for a 4+12+16 APSK signal in a nonlinear AWGN channel and propose a simple signal detection algorithm for the 4+12+16 APSK from the presented bit mapping.

• Transactions on Electrical and Electronic Materials
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• v.15 no.3
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.