• Journal of Hydrogen and New Energy
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• v.25 no.4
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• pp.386-392
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• 2014

The effective water management in a polymer electrolyte membrane fuel cell (PEMFC) is one of the key strategies for improving cell performance and durability. In this work, an ex situ measurement was carried out to understand the water droplet behavior on the surface of gas diffusion layer (GDL) as a fundamental study for establishing novel water management. For that purpose, simplified cell including one rib and two flow channels was designed and fabricated. Using this ex situ device, the water droplet emergence through the GDL of the PEMFC was emulated to understand liquid water transport through the porous diffusion medium. Through the visualization experiment, the emergence and growth of water droplets at the channel/GDL interface are mainly observed with the surface characteristics of GDL (SGL 10BA, 24BA) and rib when the liquid water passes through the GDL and is expelled to the flow channel. It is expected that the results obtained from this study can contribute to the better understanding on the water droplet behavior (emergence and removal) in the flow channels of PEMFC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.25-31
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• 2004

In this paper, we introduce kinetic Monte Carlo (kMC) methods for simulating diffusion process in nano-scale device fabrication. At first, we review kMC theory and backgrounds and give a simple point defect diffusion process modeling in thermal annealing after ion (electron) implantation into Si crystalline substrate to help understand kinetic Monte Carlo methods. kMC is a kind of Monte Carlo but can simulate time evolution of diffusion process through Poisson probabilistic process. In kMC diffusion process, instead of. solving differential reaction-diffusion equations via conventional finite difference or element methods, it is based on a series of chemical reaction (between atoms and/or defects) or diffusion events according to event rates of all possible events. Every event has its own event rate and time evolution of semiconductor diffusion process is directly simulated. Those event rates can be derived either directly from molecular dynamics (MD) or first-principles (ab-initio) calculations, or from experimental data.

• Journal of IKEEE
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• v.12 no.2
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• pp.110-117
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• 2008

This paper presents a new Insulated Gate Bipolar Transistor(IGBT) based on Non Punch Through(NPT) IGBT structure for power switching device. The proposed structure has adding N+ beside the P-base region of the conventional IGBT structure. The added n+ diffusion of the proposed device ensure device has faster turn-off time and lower forward conduction loss than the conventional IGBT structure. But, added n+ region can reduce th breakdown voltage and latching current density of the proposed device due to its high doping concentration. This problems can be overcome by using diverter on the right side of the device. In the simulation results, turn-off time of the proposed device is 0.3us and the on-state voltage drop is 3V. The results show that the proposed device has superior characteristic than conventional structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3
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• pp.459-464
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• 2013

The purpose of a micro-mixing device is to enhance the mixing by increasing the diffusion effect between different types of flows. There have been many attempts to actively or passively increase mixing. However, those studies were limited to lab-scale experiments because the production of devices requires a series of processes, time, cost, and the mixing quality itself. For this reason, this study attempted to develop a quick and simple process for micro-mixing device fabrication by using conventional machining and bonding processes and applying ultrasonic waves from the outside of the mixing device. The mixing quality was quantified by using the mixing index, and the results showed that the proposed system increases the mixing from ~33% to ~10% with respect to the flow rates.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.385-388
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• 1999

A new local model for impact ionization coefficients is proposed to account for a non-local effect. New model uses an effective electric field which comes from the path integral of a tangent electric field at an arbitrary point. The model consists of local variables, such as doping concentration, carrier concentration and gradient of the field, and can be easily applied to a conventional drift-diffusion device simulator. By comparing the results with Monte Carlo simulation, it is confirmed that new model explains the non-local effect fairly well.

• Journal of Korean Vacuum Science & Technology
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• v.6 no.1
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• pp.51-54
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• 2002

Polymer EL devices of glass/ITO/PI/MEH-PPV/Al structure were fabricated using spin coating and the Ionized Cluster Beam deposition technique. PMDA-ODA type thin polyimide films which can be used as a impurity blocking layer of EL device were deposited by ICB. According to our previous results, the packing densities of polyimide films were subject to change and depend on their deposition condition. By inserting a Pl layer with various thickness and packing density, I-V characteristics and life time of the devices were investigated to determine the role of a interlayer. The blocking of impurity diffusion from ITO to luminescent layer were confirmed by XPS.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.252.1-252.1
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• 2013

Hexagonal boron nitride (h-BN) is a two dimensional material which has high band-gap, flatness and inert properties. This properties are used various applications such as dielectric for electronic device, protective coating and ultra violet emitter so on. 1) In this report, we were growing h-BN sheet directly on sapphire 2"wafer. Ammonia borane (H3BNH3) and nickel were deposited on sapphire wafer by evaporate method. We used nickel film as a sub catalyst to make h-BN sheet growth. 2) During annealing process, ammonia borane moved to sapphire surface through the nickel grain boundary. 3) Synthesized h-BN sheet was confirmed by raman spectroscopy (FWHM: ~30cm-1) and layered structure was defined by cross TEM (~10 layer). Also we controlled number of layer by using of different nickel and ammonia borane thickness. This nickel film supported h-BN growth method may propose fully and directly growing on sapphire. And using deposited ammonia borane and nickel films is scalable and controllable the thickness for h-BN layer number controlling.