• 제목/요약/키워드: Differential amplifier

검색결과 238건 처리시간 0.023초

자기바이어스 트랜스컨덕터를 이용한 RFID 리더용 CMOS 저전압 필터 (CMOS Low-voltage Filter For RFID Reader Using A Self-biased Transconductor)

  • 정택원;방준호
    • 한국산학기술학회논문지
    • /
    • 제10권7호
    • /
    • pp.1526-1531
    • /
    • 2009
  • RFID Reader IC에 응용하기 위한 저전압 특성의 5차 일립틱 CMOS Gm-C 필터를 설계하였다. 설계된 필터는 CMOS 자기바이어스 차동 트랜스컨덕터를 설계하여 구성하였으며 차동 트랜스컨덕터는 기존의 자기 바이어스 차동증폭기의 이득특성을 개선하기 위하여 병렬형으로 구성되었다. 설계된 필터는 RFID 리더용 저전압 필터 설계사양에 따라 1.8V의 저전압으로 동작이 가능하도록 설계되었다. 1.8V, 0.18${\mu}m$CMOS 공정 파라미터를 사용하여 HSPICE 시뮬레이션 결과, 설계된 5차 일립틱 저역 필터가 설계사양인 1.35MHz의 차단주파수를 만족함을 확인하였다.

8.2-GHz band radar RFICs for an 8 × 8 phased-array FMCW receiver developed with 65-nm CMOS technology

  • Han, Seon-Ho;Koo, Bon-Tae
    • ETRI Journal
    • /
    • 제42권6호
    • /
    • pp.943-950
    • /
    • 2020
  • We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계 (The Design of 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter)

  • 정강민
    • 정보처리학회논문지A
    • /
    • 제11A권2호
    • /
    • pp.195-202
    • /
    • 2004
  • 본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다.

멀티미디어 동기화를 위한 동적 SRT 알고리즘 (Design of New CMOS Differential Amplifier Circuit)

  • 홍명희;장덕철;김우생
    • 한국통신학회논문지
    • /
    • 제18권6호
    • /
    • pp.863-870
    • /
    • 1993
  • 새로운 멀티미디어 데이터 통합 기법은 사용자가 고수준 사용자 인터페이스를 이용하여 멀티미디어 데이타들의 통합 관계를 구성하면, 시스템이 동적으로 SRT(Synchronization Relation Tree)를 구성하고, SRT에 메세지 패싱 프로토콜을 수행하여 미디어 데이타들의 통합을 이루는 방식이다. 본 논문에서는, 사용자가 정의한 타임라인 다이어그램을 시스템이 동적으로 SRT를 생성하는 알고리즘을 제안한다. SRT를 동적으로 생성하는 알고리즘은 divide and conquer 방식의 재귀적인 알고리즘 형태로 구성하여 다양한 형태의 멀티미디어 데이타 구성에도 SRT가 생성됨을 보였다.

  • PDF

Temperature Compensated Hall-Effect Power IC for Brushless Motor

  • Lee, Cheol-Woo;Jang, Kyung-Hee
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2002년도 ITC-CSCC -1
    • /
    • pp.74-77
    • /
    • 2002
  • In this paper we present a novel temperature compensated Hall effect power IC for accurate operation of wide temperature and high current drive of the motor coil. In order to compensate the temperature dependence of Hall sensitivity with negative temperature coefficient(TC), the differential amplifier has the gain consisted of epi-layer resistor with positive TC. The material of Hall device and epi-resistor is epi-layer with the same mobility. The variation of Hall sensitivity is -38% at 150$^{\circ}C$ and 88% at - 40$^{\circ}C$. But the operating point(B$\sub$op/) and release point(B$\sub$RP/) of the Hall power IC are within ${\pm}$25%. The experimental results show very stable and accurate performance over wide temperature range of -40$^{\circ}C$ to 125$^{\circ}C$.

  • PDF

근전의수용 건식형 능동 표면 근전도 전극의 개발 (Development of Dry-type Active Surface EMG Electrode for Myoelectric Prosthetic Hand)

  • 최기원;문인혁;추준욱;김경훈;문무성
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
    • /
    • pp.2733-2736
    • /
    • 2003
  • This paper proposes a dry-type active surface EMG electrode for the myoelectric prosthetic hand. The designed electrode is small size for embedding in the socket of prosthetic hand, and it has three leads including the reference of signal. To acquire EMG signal rejected the power noise, a precision differential amplifier and various filters such as the band pass filter band rejection filter, low pass and high pass filter are embedded on the electrode. The final output of the electrode is integrated absolute EMG (IEMG) obtained by full rectifier and moving average circuits. From experimental results using the implemented dry-type active surface EMG electrode, the proposed electrode is feasible for the myoelectric prosthetic hand.

  • PDF

새로운 신호처리회로와 ISFET 요소센서의 단일칩 집적 (One-Chip Integration of a New Signal Process Circuit and an ISFET Urea Sensor)

  • 서화일;손병기
    • 전자공학회논문지A
    • /
    • 제28A권12호
    • /
    • pp.46-52
    • /
    • 1991
  • A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

  • PDF

생체 근육 신호를 이용한 보철용 팔의 제어 (Prosthetic arm control using muscle signal)

  • 유재명;김영탁
    • 한국정밀공학회:학술대회논문집
    • /
    • 한국정밀공학회 2005년도 춘계학술대회 논문집
    • /
    • pp.1944-1947
    • /
    • 2005
  • In this paper, the control of a prosthetic arm using the flex sensor signal is described. The flex sensors are attached to the biceps and triceps brchii muscle. The signals are passed a differential amplifier and noise filter. And then the signals are converted to digital data by PCI 6036E ADC. From the data, position and velocity of arm joint are obtained. Also motion of the forearm - flexion and extension, the pronation and supination are abstracted from the data by proposed algorithm. A two D.O.F arm with RC servo-motor is designed for experiment. The arm length is 200 mm, weight is 4.5 N. The rotation angle of elbow joint is $120^{\circ}$. Also the rotation angle of the wrist is $180^{\circ}$. Through the experiment, we verified the possibility of the prosthetic arm control using the flex sensor signal. We will try to improve the control accuracy of the prosthetic arm continuously.

  • PDF

병렬구조의 압력측정 시스템 개발 (Development of a Pressure Measurement System with the Parallel Structure)

  • 윤의중;김좌연;이강원;이석태
    • 한국전기전자재료학회논문지
    • /
    • 제19권4호
    • /
    • pp.328-333
    • /
    • 2006
  • In this paper, we developed a pressure measurement apparatus with the parallel structure to improve the measurement efficiency of pressure sensors by reducing the measurement time of pressure. The developed system has two parallel positions for loading Silicon pressure sensor and has a dual valve structure. The semiconductor pressure sensors prepared by Copal Electronics were used to confirm the performance of the developed measurement system. Two stage differential amplifier circuit was employed to amplify the weak output signal and the amplified output signal was improved utilizing a low-pass filter. New apparatus shows the measurement time of pressure two times shorter than that of conventional one with the serial structure, while both structures show the similar linear output versus pressure characteristics.

저전력 8비트 10MS/s 파이프라인 ADC 설계 (A Design of 8bit 10MS/s Low Power Pipelined ADC)

  • 배성훈;임신일
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
    • /
    • pp.606-608
    • /
    • 2006
  • This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

  • PDF