• Journal of Power Electronics
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• v.19 no.2
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• pp.403-412
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• 2019

Aiming at the problems of large dv/dt and di/dt in traditional single-ended converters and high electromagnetic interference (EMI) noise levels, a single-ended isolated converter using the secondary resonance technique is proposed in this paper. In the proposed converter, the voltage stress of the main power switch can be reduced and the voltage across the output diode is clamped to the output voltage when compared to the conventional flyback converter. In addition, the peak current stress through the main power switch can be decreased and zero current switching (ZCS) of the output diode can be achieved through the resonance technique. Moreover, the EMI noise coupling path and an equivalent model of the proposed converter topology are presented through the operational principle of the proposed converter. Analysis results indicate that the common mode (CM) EMI noise and the differential mode (DM) EMI noise of such a converter are deduced since the frequency spectra of the equivalent controlled voltage sources and controlled current source are decreased when compared with the traditional flyback converter. Furthermore, appropriate parameter selection of the resonant circuit network can increase the equivalent impedance in the EMI coupling path in the low frequency range, which further reduces the common mode interference. Finally, a simulation model and a 60W experimental prototype of the proposed converter are built and tested. Experimental results verify the theoretical analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.6
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• pp.31-38
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• 2003

Among mitigation techniques for electric and magnetic field (EMF) from an overhead transmission line a passive loop is a way that can be cheap and easily installed on the existing towers and have a satisfactory effect as well. However current induced in the passive loop causes transmission power loss and the phase imbalance increases since geometrical asymmetry of the transmission lines becomes larger. So in order to evaluate the power loss and the phase imbalance due to a passive loop, this paper represent a 345[kV] 1-circuit flat type transmission line as asymmetrical 3-phase distributed parameter line model where the effect of a passive loop is embedded in the line parameters, and then formulates differential equations. By solving these equations voltages and currents of each phase at receiving end become known. We find out that power losses occur differently at each phase and positive sequence component decreases at receiving end while negative sequence component increase. In general phase imbalance due to a passive loop is slight, but it increases in proportional to the induced current and length of section where the passive loop is installed. Thus the phase imbalance should be included in terms of cost for introducing a passive loop.

• Journal of Biomedical Engineering Research
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• v.25 no.4
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• pp.269-275
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• 2004

Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.16-21
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• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• Journal of The Korean Association For Science Education
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• v.36 no.6
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• pp.815-833
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• 2016

This study investigated children's (grade 3 to 9) responses to assessment items on energy as a cross-cutting concept in order to get basic information for a learning progression. The assessment consisted of 8 ordered multiple-choice items at the contexts of electric circuit, mechanical energy of falling objects, phase change of matter, dissolution, biological phenomena of a lizard, food chain, radiative equilibrium between Sun and Earth, and the system of water cycling. Children's responses to each item were analyzed with using cross-tabulations in terms of grades and item option levels and Wright map and Differential item functioning based on Rasch modeled item response analysis. The results offered empirical evidence of children's development of understanding energy from relation between energy and its phenomena, types of energy, transfer and conversion of energy, towards conservation and equilibrium of energy for all of eight contexts. Children of each grade did not fully understand energy conservation. As grade goes up, their understandings of energy transfer and conversion were differentiated across the contexts and topics of energy. According to Rasch analysis, children had easier understanding of energy on dissolution and poorer understanding of energy on water cycling than that on other contexts. It was discussed and suggested that the results of this study help us organize science topics with regard to energy when developing new national science curriculum.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• Archives of design research
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• v.11 no.1
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• pp.291-302
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• 1998

This paper covers the development process of multimedia evaluation system, especially focused on customer satisfactory factors while customers navigating net-based Interactive multimedia system. Customers usually experience new level of interaction cased by newly developed web-based technology In ordinary multimedia system. However, if it gives customers satisfactory experience is a matter of question. To find out the relationship between customer satisfaction and interactivity factors exposed by multimedia system, a model has been developed which describes the structure of web-based multimedia system and its relation to customer satisfactory factors. Five different experiments, including 'semantic differential', 'focus group interview', and 'expert review', has been conducted and four customer satisfactory factors were identified. Those are 'customery value', 'structural perfectness', 'visual perfectness', and 'contemporaneity'. With these factors and newly delveoped evaluation system, 7 different web-site has been evaluated and analyzed at the end of this report.