• 전자공학회논문지D
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• 제34D권12호
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• pp.89-100
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• 1997

This paper investigated a new type of low voltage threshold switch (LVTS). As distinguished from the many other types of electronic threshold switches, the LvTS is ; voltage controlled, occurs at low voltages ($V_{2}$ $O_{5}$lV devices. The average low threshold voltage < $V_{LVT}$>=218 mV (standard deviation =24mV~kT/q, where T=300K), and was independent of the device area (x100) and amorphous oxide occurred in an ~22.angs. thick interphase of the V/amorphous- $V_{2}$ $O_{5}$ contacts. At $V_{LVT}$ there was a transition from an initially low conductance (OFF) state into a succession of quantized states of higher conductance (ON). The OFF state was spatically homogeneous and dominated by tunneling into the interphase. The ON state conductances were consistent with the quantized conductances of ballistic transport through a one dimensional, quantum point contact. The temeprature dependence of $V_{LVT}$, and fit of the material parameters (dielectric function, barrier energy, conductivity) to the data, showed that transport in the OFF and ON states occurred in an interphase with the characteristics of, respectively, semiconducting and metallic V $O_{2}$. The experimental results suggest that the LVTS is likely to be observed in interphases produced by a critical event associated with an inelastic transfer of energy.rgy.y.rgy.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.193-193
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• 2011

To obtain ceramic films, the sol-gel coating technique has been broadly used with heat treatment, but crack formation tend to occur during heat treatment in thick sol-gel films. We prepared PZT thin films by sol-gel method with single-step spin coating process. The PZT solution have been synthesized using lead acetate ($Pb(CH_3COO)_2$), zirconium acetylacetonate ($Zr(OC_3H_7^n)_4$), and titanium diisopropoxide bis(acetylacetonate) 75wt% in isopropanol ($Ti(OC_3H_7^i)_2(OC_3H_7^n)_2$) as starting materials and n-propanol was selected as a solvent. The poly(vynilpyrrolidone) (PVP) was added with 0, 0.25, 0.5, 0.75, and 1 molar ratios to control viscosity of solution. We investigated influence of the viscosity on thickness, microstructure, and electrical properties of final PZT films. Thermo-gravimetric analysis and differential scanning calorimeter (TGA/DSC) was carried out from room temperature to $800^{\circ}C$ in order to measure pyrolysis temperature. Structural characteristics were analyzed by X-ray diffraction (XRD) and scanning electron microscopy (SEM). Ferroelectric and dielectric properties were measured by RT66A (Radiant) and impedance analyzer (Agilent), respectively. The thicknesses of PZT films depended on incorporation of an excess amount of PVP. Finally, we obtained PZT films of good quality without crack formation via single-step spin coating.

• 한국전기전자재료학회논문지
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• 제27권12호
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• pp.852-856
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• 2014

$BaTiO_3$ nano powder can be synthesized by hydrate salt method at $120^{\circ}C$ in air. Decreasing the thickness of thick film, the nano dielectric particle is needed in electronic ceramics. However, the synthesis of $BaTiO_3$ nano particle at low temperature in air and their mechanism were not reported enough. And ultrasonic treatment can be tried because of low temperature process in air. Therefore, in this study, the $BaTiO_3$ nano powder was synthesised with the synthesis time and ultrasonic treatment at $120^{\circ}C$ in air. In the synthesis process, the effects of process were evaluated. From the experimental observation, the synthesis mechanism was proposed. The homogeneous $BaTiO_3$ particle was synthesised by KOH salt solution at $120^{\circ}C$ for 1hour. It was conformed that the ultrasonic treatment effected on the increase of synthesis rate. After cutting the salt powder using FIB, $BaTiO_3$ nano particles observed homogeneously in the cross-section of the salt particle.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국결정성장학회지
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• 제4권4호
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• pp.378-387
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• 1994

선행연구[1] 즉, $Ti0_2/Pb/TiO_2(900{\AA}/900{\AA}/900{\AA}/)$ 3층구조박막으로부터 열확산에 의해 상형성이 가능하였던 $PbTiO_3$ 박막의 특성을 개선하기 위하여 스퍼터링법을 이용하여 Si기판위에 각 요소층의 두께를 $200~300 {\AA}$으로 얇게하고 적층수를 3,5,7,9,11층$(TiO_2/Pb/.../Tio_2)$으로 변화시켜가며 다층구조박막을 형성한 후 이를 RTA 처리하여 $PbTiO_3$ 박막을 제조하였다. 그 결과 $500^{\circ}C$ 이상에서 단일상의 $PbTiO_3$가 형성되었다. 또한 요소층의 두께를 얇게하고 적층수를 늘려서 열처리한 결과 Pb-silicate 및 void 생성이 억제되어 우수한 계면상태를 유지하였으며 조성도 보다 균일해지는 양상을 나타내었다. $PbTiO_3$ 박막의 MiM구조에 C-V 특성으로부터 측정된 유전상수는 열처리 조건에 따른 경향을 나타내지 않았으나 적층수가 많아져 박막의 두께가 증가 할수록 유전상수가 증가하였다. MIS 구조의 $PbTiO_3$ 박막의 I-V 특성 측정 결과 절연파괴강도는 최고 150kV/cm이었다.

• 전자공학회논문지D
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• 제36D권10호
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• pp.9-16
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• 1999

Flash EEPROM 셀에서 기존의 ONO 구조의 IPD를 사용하면 peripheral MOSFET의 게이트 산화막을 성장할 때에 사용되는 세정 공정을 인하여 ONO 막의 상층 산화막이 식각되어 전하 보존 특성이 크게 열화되었으나 IPD 공정에 ONON 막을 사용하면 그 세정 공정시에 상층 질화막이 상층 산호막이 식각되는 것을 방지시켜 줌으로 전하보존 특성이 크게 개선되었다. ONON IPD 막을 갖고 있는 Flash EEPROM 셀의 전화 보존 특성의 모델링을 위하여 여기서는 굽는(bake) 동안의 전하 손실로 인한 문턱전압 감소의 실험식으로 ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$을 사용하였으며, 측정 결과 ${\beta}$=184.7, m=0.224, Ea=0.31 eV의 값을 얻었다. 이러한 0.31 eV의 활성화 에너지 값은 굽기로 인한 문턱전압의 감소가 층간 질화막 내에서의 트립된 전자들의 이동에 의한 것임을 암시하고 있다. 한편, 그 모델을 사용한 전사 모사의 결과는 굽기의 thermal budget이 낮은 경우에 실험치와 잘 일치하였으나, 반면에 높은 경우에는 측정치가 전사 모사의 결과보다 훨씬 더 크게 나타났다. 이는 thermal budge가 높은 경우에는 프로그램시에 층간 질화막 내에 트립되어 누설전류의 흐름을 차단해 주었던 전자들이 빠져나감으로 인하여 터널링에 의한 누설전류가 발생하였기 때문으로 보여졌다. 이러한 누설전류의 발생을 차단하기 위해서는 ONON 막 중에서 층간 질화막의 두께는 가능한 얇게 하고 상층 산화막의 두께는 가능한 두껍게 하는 것이 요구된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 마이크로전자및패키징학회지
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• 제28권3호
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• pp.33-38
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• 2021

최근 유연 디스플레이에 관한 대중의 관심이 증대됨에 따라 롤러블(rollable), 폴더블(foldable) 디스플레이와 같은 우수한 폼 팩터(form factor)를 지닌 차세대 유연(flexible) 디스플레이가 주목받고 있다. 유연 디스플레이의 기계적 신뢰성 확보 측면에서, 내부 절연막으로 활용되는 실리콘 질화물(SiN_x) 박막은 구동 중 발생하는 응력에 매우 취약하므로 기계적 물성을 정확히 파악하여 파손을 예측하고 패널의 전기적 단락을 방지하는 것이 중요하다. 본 논문에서는, ~130 nm, ~320 nm 두께의 SiN_x 박막 박막 상부에 ~190 nm 두께의 유기 나노 보강층(PMMA, PS, P3HT)을 코팅하여 이중층 구조로 인장함으로써 매우 취성한 SiN_x 박막의 탄성 계수와 인장 강도 및 연신율을 측정하는 데 성공하였다. 챔버 압력 및 증착 파워를 조절한 공정 조건(A: 1250 mTorr, 450 W/B: 1000 mTorr, 600 W/C: 750 mTorr, 700 W)을 통해 제작된 ~130 nm SiN_x 의 탄성계수는 A: 76.6±3.5, B: 85.8±4.6, C: 117.4±6.5 GPa로, ~320 nm SiN_x는 A: 100.1±12.9, B: 117.9±9.7, C: 159.6 GPa로 측정되었다. 결과적으로, 동일 공정 조건 하에서 SiN_x 박막의 두께가 증가할수록 탄성 계수가 증가하는 경향을 확인하였으며, 유기 나노 보강층을 활용한 인장 시험법은 파손되기 쉬운 취성 박막의 기계적 물성을 높은 정밀도로 측정하는 데 효과적이었다. 본 연구에서 개발된 방법은, 취약한 디스플레이용 박막의 정량적인 기계적 물성 파악을 가능케하여 강건한 롤러블, 폴더블 디스플레이의 설계에 이바지할 수 있을 것으로 기대한다.

• 한국전기전자재료학회논문지
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• 제17권1호
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• pp.7-15
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• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.

• 한국진공학회지
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• 제15권4호
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• pp.395-403
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• 2006

[ $MgAl_2O_4$ ] 막은 MgO 보호막 보다 단단하며 수분 흡착 오염 문제에 상당히 강한 특성을 가진다. 본 연구에서 AC-PDP 의 유전체보호막으로 사용되는 MgO 보호막의 특성을 개선하기 위해 $MgAl_2O_4/MgO$ 이중층 보호막을 제작하여 특성을 조사하였다. 전자빔 증착기를 사용하여 Cu 기판에 MgO 와 $MgAl_2O_4$을 각각 $1000\AA$ 두께로 증착, $MgAl_2O_4/MgO$ 을 $200/800\AA$ 두께로 적층 증착 후, 이온빔에 의한 충전현상을 제거하기 위해 Al 을 $1000\AA$ 두께로 증착하였다. 집속 이온빔 (focused ion beam: FIB) 장치를 이용하여 10 kV 에서 14 kV 까지 이온빔 에너지에 따라 MgO는 $0.364{\sim}0.449$ 값의 스퍼터링 수율에서 $MgAl_2O_4/MgO$ 을 적층함으로 $24{\sim}30 %$ 낮아진 $0.244{\sim}0.357$ 값의 스퍼터링 수율이 측정되었으며, $MgAl_2O_4$는 가장 낮은 $0.088{\sim}0.109$ 값의 스퍼터링 수율이 측정되었다. g-집속이온빔 (g-FIB) 장치를 이용하여 $Ne^+$ 이온 에너지를 50 V 에서 200 V 까지 변화시켜 $MgAl_2O_4/MgO$ 와 MgO 는 $0.09{\sim}0.12$의 비슷한 이차 전자방출 계수를 측정하였다. AC- PDP 셀의 72 시간 열화실험 후 SEM 및 AFM으로 열화된 보호막의 표면을 관찰하여 기존의 단일 MgO 보호막과 $MgAl_2O_4/MgO$의 적층보호막의 열화특성을 살펴보았다.