• Title/Summary/Keyword: Dielectric layers

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Electrical Properties of Heterolayered PZT/PT Thick Films (이종층 PZT/PT 후막의 전기적 특성)

  • Nam, Sung-Pil;Lee, Sung-Gap;Bae, Seon-Gi;Lee, Young-Hie
    • Proceedings of the KIEE Conference
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    • 2008.05a
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    • pp.169-170
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    • 2008
  • The heterolayered PZT/PT thick films were fabricated by two different methods - thick films of the PZT by screen printing method on alumina substrates electrodes with Pt, thin films of $PbTiO_3$ by the spin coating method on the PZT thick films and once more thick films of the PZT by the screen printing method on the $BaTiO_3$ layer The structural and the dielectric properties were investigated for effect of various stacking sequence of sol-gel prepared $PbTiO_3$ coating solution at interface of the PZT thick films. The insertion of $PbTiO_3$ interlayer yielded the PZT thick films with homogeneous and dense grain structure with the number of $PbTiO_3$ layers. The leakage current density of the PZT/$PbTiO_3-1$ film is less that $4.41{\times}10^{-9}\;A/cm^2$ at 5 V.

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Electric Field Analysis of Power Cable Joint Point using Boundary Element Method (경계요소법을 이용한 전력케이블 접속부의 전계해석)

  • 조경순
    • Journal of the Korea Computer Industry Society
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    • v.4 no.4
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    • pp.579-588
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    • 2003
  • There are many unfavorable conditions that lead to shortening life of cable by causing dielectric breakdown and aging such as field concentrations occurring in intermediate materials linking each cables, penetration of various impurities, and undermining of cable insulation layers. This paper simulated investigated partial discharge properties of XLPE which is widely used for ultra high voltage cable insulation materials and EPDM which is being used as insulation layer of cable joint materials kit, using Boundary Element Method. The result of computer simulation showed that inner-Void defect caused silicone oil to weaken the E-field effect. and we also found that E-field distribution in EPDM remained relatively lower than that in XLPE.

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Fabrications and properties of MFIS capacitor using SiON buffer layer (SiON buffer layer를 이용한 MFIS Capacitor의 제작 및 특성)

  • 정상현;정순원;인용일;김광호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.70-73
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    • 2001
  • MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

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Growth and Characteristics of NO/$N_2$O Oxynitrided and Reoxidized Gate Dielectrics for Charge Trapping NVSMs (산화막의 NO/$N_2$O 질화와 재산화 공정을 이용한 전하트랩형 NVSM용 게이트 유전막의 성장과 특성)

  • 윤성필;이상은;김선주;서광열;이상배
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.11a
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    • pp.9-12
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    • 1998
  • Film characteristics of thin reoxidized nitrided oxides were investigated by SIMS analysis and C-V method in order to use the gate dielectric for charge-trap type NVSMs instead of ONO stacked layers. Nitric oxide(NO) annealed film has the nitrogen content sharply peaked at the Si-SiO$_2$ interface, while it is broad for nitrous oxide($N_2$O) ambient. The nitrogen peak concentration increased with anneal temperature and time. The position of nitrogen content in the oxide layer was due to be precisely controlled. For the films annealed NO ambient at 80$0^{\circ}C$ for 30min. followed by reoxidized at 85$0^{\circ}C$, the maximum memory window of 3.5V was obtained and the program condition was +12V, 1msec for write and -l3V, 1msec for erase.

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ADHESION PHENOMENON AND ITS APPLICATION TO MANIPULATION FOR MICRO-ASSEBMLY

  • Takahashi, Kunio;Himeno, Hideo;Saito, Shigeki;Onzawa, Tadao
    • Proceedings of the KWS Conference
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    • 2002.10a
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    • pp.781-784
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    • 2002
  • Adhesion phenomenon is more significant for smaller objects, because adhesional force is proportional to size of the objects while gravitational force is proportional to the third power of it. For the purpose of microassembly, theoretical understanding is required for the Adhesion phenomenon. Authors have developed a force measurement system in an ultra-high vacuum chamber of Auger electron spectroscopy. The force between arbitrary combination of materials can be measured at a pressure less than 100 nPa after and before Ar ion sputtering and chemical analysis for several atomic layers of the surface. The results are successfully interpreted with a theory of contact mechanics. Since surface energy is quite important in the interpretation, electronic theory is used to evaluate the surface energy. In the manipulation of small objects, the adhesional force is always attractive. Repulsive force is essential for the manipulation. It can be generated by Coulomb interaction. The voltage required for detachment is theoretically analyzed and the effect of boundary conditions on the detachment is obtained. The possibility and limitations of micro-manipulation using both the adhesion phenomenon and Coulomb interaction are theoretically clarified. Its applicability to nano-technology is found to be expected.

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Formation of $PbTiO_3$ Thin Films by Thermal Diffusion from Multilayrs (다층 구조로부터 열 확산에 의한 $PbTiO_3$ 박막의 제조)

  • 서도원;최덕균
    • Journal of the Korean Ceramic Society
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    • v.30 no.6
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    • pp.510-516
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    • 1993
  • $PbTiO_3$ thin films have been formed by rapid thermal annealing(RTA) of $TiO_2$/Pb/$TiO_2$ multilayer films deposited on Si wafers by RF sputtering. Based on the optimal depositon conditions of TiO2 and Pb, $TiO_2$/Pb/$TiO_2$ three layers were deposited for 900$\AA$ each. These films were subjected to RTA process at the temperatures ranging from $400^{\circ}C$ to $900^{\circ}C$ for 30 seconds in air, and were analyzed by X-ray diffraction and transmission electron microscopy to investigate the phases and the microstructures. As a result, perovskite $PbTiO_3$ phases was obtained above $500^{\circ}C$ with the trace of unreacted $TiO_2$. RBS analysis revealed the anisotropic behavior of diffusion that the diffusivity of Pb to the bottom $TiO_2$ layer was faster than that of Pb to the top $TiO_2$ layer. The amorphous Pb-silicate was formed between film and Si substrate due to the diffusion of Pb, but Pb-silicate existed locally at the interface and the amount of that phase was very small. Therefore the effect of bottom $TiO_2$ layer as a diffusion barrier was confirmed. $PbTiO_3$ films formed by current technique showed a relative dielectric constant of 60, and the maximum breakdown field reached 170kV/cm.

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Effects of Stress Mismatch on the Electrical Characteristics of Amorphous Silicon TFTs for Active-Matrix LCDs

  • Lee, Yeong-Shyang;Chang, Jun-Kai;Lin, Chiung-Wei;Shih, Ching-Chieh;Tsai, Chien-Chien;Fang, Kuo-Lung;Lin, Hun-Tu;Gan, Feng-Yuan
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.729-732
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    • 2006
  • The effect of stress match between silicon nitride ($SiN_2$) and hydrogenated amorphous silicon (a-Si:H) layers on the electrical characteristics of thin-film transistors (TFTs) has been investigated. The result shows that modifying the deposition conditions of a Si:H and $SiN_2$ thin films can reduce the stress mismatch at a-Si:H/SiNx interface. Moreover, for best a-Si:H TFT characteristics, the internal stress of gate $SiN_2$ layer with slightly nitrogen-rich should be matched with that of a-Si:H channel layer. The ON current, field-effect mobility, and stability of TFTs can be enhanced by controlling the stress match between a-Si:H and gate insulator. The improvement of these characteristics appears to be due to both the decrease of the interface state density between the a-Si:H and SiNx layer, and the good dielectric quality of the bottom nitride layer.

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2.2 inch qqVGA AMOLED drived by ultra low temperature poly silicon (ULTPS) TFT direct fabricated below $200^{\circ}C$

  • Kwon, Jang-Yeon;Jung, Ji-Sim;Park, Kyung-Bae;Kim, Jong-Man;Lim, Hyuck;Lee, Sang-Yoon;Kim, Jong-Min;Noguchi, Takashi;Hur, Ji-Ho;Jang, Jin
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.309-313
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    • 2006
  • We demonstrated 2.2inch qqVGA AMOLED display drived by ultra low temperature poly-Si (ULTPS) TFT not transferred but direct fabricated below $200^{\circ}C$. Si channel was crystallized by decreasing impurity concentration even at room temperature. Gate insulator with a breakdown field exceeding 8 MV/cm was realized by Inductively coupled plasma - CVD. In order to reduce stress of plastic, organic film was coated as inter-dielectric and passivation layers. Finally, ULTPS TFT of which mobility is over $20cm^2/Vsec$ was fabricated on transparent plastic substrate and drived OLED display successfully.

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Fabrication and Properties of Metal/Ferroelectrics/Insulator/Semiconductor Structures with ONO buffer layer (ONO 버퍼층을 이용한 Metal/Ferroelectrics/Insulator/Semiconductor 구조의 제작 및 특성)

  • 이남열;윤성민;유인규;류상욱;조성목;신웅철;최규정;유병곤;구진근
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.305-309
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    • 2002
  • We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

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Characteristic of Oxide CMP with the Various Temperatures of Silica Slurry (실리카 슬러리의 온도 변화에 따른 산화막의 CMP 특성)

  • Ko, Pil-Ju;Park, Sung-Woo;Kim, Nam-Hoon;Seo, Yong-Jin;Chang, Eui-Goo;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.707-710
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    • 2004
  • Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-level dielectrics (ILD). In this paper, we have investigated slurry properties and CMP performance of silicon dioxide (oxide) as a function of different temperature of slurry. Thermal effects on the silica slurry properties such as pH, particle size, conductivity and zeta potential were studied. Moreover, the relationship between the removal rate (RR) with WIWNU and slurry properties caused by changes of temperature were investigated. Therefore, the understanding of these temperature effects provides a foundation to optimize an oxide CMP Process for ULSI multi-level interconnection technology.

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