• 로봇학회논문지
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• 제11권2호
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• pp.100-107
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• 2016

To realize a robot hand interacting like a human hand, there are many tactile sensors sensing normal force, shear force, torque, shape, roughness and temperature. This sensing signal is essential to manipulate object accurately with robot hand. In particular, slip sensors make manipulation more accurate and breakless to object. Up to now several slip sensors were developed and applied to robot hand. Many of them used complicate algorithm and signal processing with vibration data. In this paper, we developed novel principle slip sensor using separation layer. These two layers are moved from each other when slip occur. Developed sensor can sense slip signal by measuring this relative displacement between two layers. Also our principle makes slip signal decoupled from normal force and shear force without other sensors. The sensor was fabricated using the NBR(acrylo-nitrile butadiene rubber) and the Ecoflex as substrate and a paper as dielectric. To verify our sensor, slip experiment and normal force decoupling test were conducted.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.370-371
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• 2006

Maxwell displacement current (MDC) measurement has been employed to study the dielectric property of Langmuir-films. MDC flowing across monolayers is analyzed using a rod-like molecular model. A linear relationship between the monolayer compression speed and the molecular area Am. Compression speed was about 30, 40, 50mm/min. Langmuir-Blodgett(LB)layers of Arachidic acid deposited by LB method were deposited onto slide glass as Y-type film. The structure of manufactured device is Au/Arachidic acid/Al, the number of accumulated layers are 9~21. Also, we then examined of the Metal-Insulator-Metal(MIM) device by means of I-V. The I-V characteristics of the device are measured from -3 to +3[V]. The insulation property of a thin film is better as the distance between electrodes is larger.

• Archives of Metallurgy and Materials
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• 제65권3호
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• pp.1063-1067
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• 2020

Dynamic charge carrier transport behavior in the zirconium (Zr) oxide was investigated based on the frequency-dependent capacitance-voltage (C-V) and temperature-dependent current-voltage (I-V) measurements. The Zr oxide was formed on the ZIRLO and newly developed zirconium-based alloy (NDZ) by corrosion in the PWR-simulated loop at 360℃. The corrosion test for 90 days showed that the NDZ exhibits better corrosion resistance than ZIRLO alloy. Based on the C-V measurement, dielectric constant values for the Zr oxide was estimated to be 11.28 and 11.52 for the ZIRLO and NDZ. The capacitance difference between low and high frequency was larger in the ZIRLO than in the NDZ, which was attributed to more mobile electrical charge carriers in the oxide layer on the ZIRLO alloy. The current through the oxide layers on the ZIRLO increased more drastically with increasing temperature than on the NDZ, which indicating that more charge trap sites exist in the ZIRLO than in NDZ. Based on the dynamic charge carrier transport behavior, it was concluded that the electrical charge carrier transport within the oxide layers was closely related with the corrosion behavior of the Zr alloys.

• 한국결정성장학회지
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• 제4권4호
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• pp.378-387
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• 1994

선행연구[1] 즉, $Ti0_2/Pb/TiO_2(900{\AA}/900{\AA}/900{\AA}/)$ 3층구조박막으로부터 열확산에 의해 상형성이 가능하였던 $PbTiO_3$ 박막의 특성을 개선하기 위하여 스퍼터링법을 이용하여 Si기판위에 각 요소층의 두께를 $200~300 {\AA}$으로 얇게하고 적층수를 3,5,7,9,11층$(TiO_2/Pb/.../Tio_2)$으로 변화시켜가며 다층구조박막을 형성한 후 이를 RTA 처리하여 $PbTiO_3$ 박막을 제조하였다. 그 결과 $500^{\circ}C$ 이상에서 단일상의 $PbTiO_3$가 형성되었다. 또한 요소층의 두께를 얇게하고 적층수를 늘려서 열처리한 결과 Pb-silicate 및 void 생성이 억제되어 우수한 계면상태를 유지하였으며 조성도 보다 균일해지는 양상을 나타내었다. $PbTiO_3$ 박막의 MiM구조에 C-V 특성으로부터 측정된 유전상수는 열처리 조건에 따른 경향을 나타내지 않았으나 적층수가 많아져 박막의 두께가 증가 할수록 유전상수가 증가하였다. MIS 구조의 $PbTiO_3$ 박막의 I-V 특성 측정 결과 절연파괴강도는 최고 150kV/cm이었다.

• 한국통신학회논문지
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• 제28권11A호
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• pp.883-890
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• 2003

본 논문에서는 접지된 유전체평면 위에 변하는 저항율을 갖는 저항띠 격자구조의 전자파 산란문제를 수치해석 방법인 FGMM(Fourier-Galerkin Moment Method)을 이용하여 스트립 폭 및 주기, 유전체층의 비유전율 및 두께, 입사각에 따라 수치 해석하였다. 산란전자계는 Floquet 모드함수의 급수로 전개하였다. 경계조건은 미지의 계수를 구하기 위하여 적용하였고, 저항띠 경계조건은 접선성분의 전계와 스트립의 유도전류와의 관계를 위해 이용하였다. 저항띠의 변하는 저항율은 저항띠의 양끝에서 0으로 변하는 경우를 취급하였고, 이때 유도되는 표면 전류밀도는 2종 Chebyshev 다항식의 급수로 전개하였다. 본 논문에서 변하는 저항율이 0을 갖는 도체띠에 대한 정규화 된 반사전력은 기존 논문의 결과와 매우 잘 일치하였다.

• 한국진공학회지
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• 제9권2호
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• pp.162-166
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• 2000

플라즈마 화학증착법(Plasma Enhanced Chemical Vapor Deposition, PECVD)을 이용하여 양질의 $Si_3N_4$ 금속-유전막-금속(Metal-Insulator-Metal, MIM) 커패시터를 구현하였다. 유전체인 $Si_3N_4$와 전극인 Al의 계면반응을 억제시키기 위해 티타늄 나이트라이드(TiN)를 확산 장벽으로 사용한 결과 MIM 커패시터의 전극과 유전체 사이의 계면에서는 어떠한 hillock이나 석출물도 관찰되지 않았다. 커패시턴스와 전류전압 특성분석으로부터 양질의 MIM 커패시터 특성을 보이는 $Si_3N_4$의 최소 두께는 500 $\AA$이며, 그 두께 미만에서는 대부분의 커패시터가 전기적으로 단락되어 웨이퍼 수율이 낮아진다는 사실을 알 수 있었다. 투과전자현미경(transmission Electron Microscope, TEM)을 이용한 단면 미세구조 관찰을 통해 $Si_3N_4$층의 두께가 500 $\AA$ 미만인 커패시터의 경우에 TiN과 $Si_3N_4$의 계면에서 형성되는 슬릿형 공동(slit-like void)01 의해 커패시터의 유전특성이 파괴된다는 사실을 알게 되었으며, 열 유기 잔류 응력(thermally-induced residual stress) 계산에 기초하여 공동의 형성 기구를 규명하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.47-52
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• 2002

A processing method is developed for preparing sol-gel derived $Pb(Zr_{1-x}Ti_x)O_3$ (x=0.5) thin films on Pt-Ir($Pt_{80}Ir_{20}$)-alloy substrates. The as-deposited layer was dried on a plate in air at $70^{\circ}C$. And then it was baked at $1500^{\circ}C$, annealed at $450^{\circ}C$ and finally annealed for crystallization at various temperatures ranging from $580^{\circ}C$ to $700^{\circ}C$ for 1hour in a tube furnace. The thickness of the annealed film with three layers was $0.3{\mu}m$. Crystalline properties and surface morphology were examined using X-ray diffractometer (XRD). Electrical properties of the films such as dielectric constant, C-V, leakage current density were measured under different annealing temperature. The PZT thin film which was crystallized at $600^{\circ}C$ for 60minutes showed the best structural and electrical dielectric constant is 577. C-V measurement show that $700^{\circ}C$ sample has window memory volt of 2.5V and good capacitance for bias volts. Leakage current density of every sample show $10^{-8}A/cm^2$ r below and breakdown voltage(Vb) is that 25volts.

• 한국진공학회지
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• 제11권3호
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• pp.166-170
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• 2002

$BaTiO_3$(BTO)/$SrTiO_3$(STO) 산화물 인공 초격자가 MgO(100) 단결정 기판위에 Pulsed laser deposition(PLD)법으로 증착되었다. 다층구조에서 BTO/STO 층의 적층 주기는 $BTO_{1\;unit\; cell}/STO_{1\;unit\; cell}$에서 $BTO_{125\;unit\; cell}/STO_{125 \;unit \;cell}$ 두께로 변화시켰고 초격자 전체 두께는 100 m으로 고정시켰다. X-ray 회절 결과는 다양한 주기의 BTO/STO 산화물 박막에서 초격자의 특성을 보였고 투과형 전자 현미경을 통해서 BTO와 STO의 두 층간의 계면에서 상호확산이 일어나지 않고 초격자가 잘 성장된 것을 확인하였다. 초격자의 유전율은 임계 두께 내에서 적층주기가 감소함에 따라 증가하였다. 이러한 초격자의 유전율은 낮은 주기 즉 $BTO_{2\;unit\; cell}/STO_{2\;unit\; cell}$ 주기에서 1230으로 높게 나왔으며 이러한 원인은 격자 변형(c/a ratio)에 기여된 것으로 분석되었다.

• 한국세라믹학회지
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• 제46권2호
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• pp.200-210
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• 2009

It is necessary to minimize the mismatch of sintering shrinkage between dielectric ceramic and Ni inner electrode layers for the purpose of developing the ultra high-capacity multi layered ceramic condenser(MLCC). Thus, low temperature sintering of dielectric $BaTiO_3$ ceramic should be precedently investigated. In this work, the influence of the milling condition on sintering behavior and electrical properties of $BaTiO_3$ ceramics was investigated in the $BaTiO_3$(BT)-Mg-Dy-Mn-Ba system with borosilicate glass as a sintering agent. As milling time increased, specific surface area(SSA) of the powder increased linearly, while both sinterability and dielectric property were found to be drastically decreased with an increasing SSA. It was also revealed that the sinterability of the excessively milled $BaTiO_3$ ceramics could be recovered by increasing Ba content, rather than increasing glass addition. These results suggest that the sintering behavior of $BaTiO_3$ ceramics under the high SSA was more strongly dependent on the transient liquid phase caused by Ba addition, than the liquid phase from additional glass.

• 한국재료학회지
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• 제17권2호
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• pp.96-99
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• 2007

The effects of post-annealing of high-k $HfO_2$ thin films grown by atomic layer deposition method were investigated by the annealing treatments of $400-600^{\circ}C$. $Pt/HfO_2/p-Si\;MOS$ capacitor structures were fabricated, and then the capacitance-voltage and current-voltage characteristics were measured to analyze the electrical characteristics of dielectric layers. The X-ray diffraction analyses revealed that the $500^{\circ}C-annealed\;HfO_2$ film remained to be amorphous, and the $600^{\circ}C-annealed\;HfO_2$ film was crystallized. The annealing treatment at $500^{\circ}C$ resulted in the highest capacitance and the lowest leakage current due to the reduction of defects in the $HfO_2$ films and non-crystallization. Our results suggest that post-annealing treatments are a critical factor in improving the characteristics of gate dielectric layer.