• 제목/요약/키워드: Dielectric layers

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Sol-Gel법으로 제작한 PZT(20/80)/PZT(80/20) 이종층 박막의 구조 및 유전특성 (Structural and Dielectric Properties of PZT(20/80)/PZT(80/20) Heterolayered Thin Films Prepared by Sol-Gel Method.)

  • 심광택;정장호;이영희;박인길;이성갑
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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    • pp.245-247
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    • 1996
  • The ferroelectric $Pb(Zr_xTi_{1-x})O_3$ (20/80, 80/20) heterolayered thin films were fabricated from an alkoxide-based by Sol-Gel method. The PZT(20/80) and PZT(80/20) stock solution were made and spin-coated on the Pt/Ti/$SiO_2$/Si substrate by turns. Each layers were baked to remove the organic materials at 300[$^{\circ}C$] for 30[min]. and sintered at 650[$^{\circ}C$] for 1[hr]. This procedure was repeated 5 times. At this time the thickness of thin films were about 4000[$\AA$]. Relative dielectric constant and remanent polarization of the PZT heterolayered thin films were 1200, 27.10 [${\mu}C/cm^2$], respectively.

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접지평면위에 2개의 유전체층을 가지는 도체띠 격자구조에서의 전자파산란 해석 (Analysis of the Electromagnetic Scattering by Conducting Strip Gratings with 2 Dielectric Layers)

  • 김용연;방성일
    • 한국산업정보학회논문지
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    • 제4권1호
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    • pp.102-109
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    • 1999
  • 본 논문에서는 접지평면위에 2개의 유전체 층을 가지는 완전도체 격자구조에서의 전자파 산란문제를 간단한 방수치해석 방법으로 잘 알려진 PMM방법을 적용하여 입사각에 따라 수치해석하였다. 산란전자계는 Floquet 모드 함수의 급수로 전개하였다. 경계조건은 미지의 계수를 구하기 위하여 적용하였고, 도체의 경계조건은 접선성분의 전계와 스트립 위의 전류와의 관계를 위해 적용하였다. 입사각이 수직일 때 비유전율이 증가함에 따라 기하광학적 반사전력의 변하는 최소점은 스트립 폭이 높은 값으로 이동한다는 것은 주목되며, 이때 수직입사시 대부분의 전력은 다른 각도의 방향으로 산란된다.

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Comparative Measurements and Characteristics of Cu Diffusion into Low-Dielectric Constant para-xylene based Plasma Polymer Thin Films

  • Kim, K.J.;Kim, K.S.;Jang, Y.C.;Lee, N.-E.;Choi, J.;Jung, D.
    • 한국표면공학회지
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    • 제34권5호
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    • pp.475-480
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    • 2001
  • Diffusion of Cu into the low-k para-xylene based plasma polymer (pXPP) thin films deposited by plasma-enhanced chemical vapor deposition using the para-xylene precursor was comparatively measured using various methods. Cu layer was deposited on the surfaces of pXPPs treated by $N_2$ plasma generated in a magnetically enhanced inductively coupled plasma reactor. Diffusion characteristics of Cu into pXPPs were measured using Rutherford backscattering spectroscopy (RBS), secondary ion mass spectroscopy (SIMS), cross-sectional transmission electron microscopy (XTEM), and current-voltage (I-V) measurements for the vacuum-annealed Cu/pXPPs for 1 hour at $450^{\circ}C$ and were compared. The results showed a correlation between the I-V measurement and SIMS data are correlated and have a sensitivity enough to evaluate the dielectric properties but the RBS or XTEM measurements are not sufficient to conclude the electrical properties of low-k dielectrics with Cu in the film bulk. The additional results indicate that the pXPP layers are quite resistant to Cu diffusion at the annealing temperature of $450^{\circ}C$ compared to the other previously reported organic low-k materials.

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알루미늄 판상에 글라스 세라믹 후막이 코팅된 절연금속기판의 제조 및 절연특성 (Fabrication and Electrical Insulation Property of Thick Film Glass Ceramic Layers on Aluminum Plate for Insulated Metal Substrate)

  • 이성환;김효태
    • 마이크로전자및패키징학회지
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    • 제24권4호
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    • pp.39-46
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    • 2017
  • 본 연구는 평판형 히터용 금속방열판상의 세라믹 절연층 제조, 즉 절연성 금속기판에 관한 것이다. 반도체나 디스플레이의 열처리 공정 등에 사용되는 평판형 히터를 제조함에 있어서, 온도 균일도를 높이기 위해 금속 방열판으로서 열전도율이 높고, 비교적 가벼우며, 가공성 좋은 알루미늄 합금 기판이 선호된다. 이 알루미늄 기판에 발열 회로 패턴을 형성하기 위해서는 금속 기판에 절연층으로서 고온 안정성이 우수한 세라믹 유전체막을 코팅하여야 한다. 금속 기판상에 세라믹 절연층을 형성함에 있어서 가장 빈번히 발생하는 첫 번째 문제는 금속과 세라믹의 이종재료 간의 큰 열팽창계수 차이와 약한 결합력에 의한 층간박리 및 균열발생이다. 두 번째 문제는 절연층의 소재 및 구조적 결함에 따른 절연파괴이다. 본 연구에서는 이러한 문제점 해소를 위해 금속소재 기판과 세라믹 절연층 사이에 완충층을 도입하여 이들 간의 기계적 매칭과 접합력 개선을 도모하였고, 다중코팅 방법을 적용하여 절연막의 품질과 내전압 특성을 개선하고자 하였다.

전해 콘텐사용 알루미늄박의 애칭특성에 미치는 황산첨가의 영향 II. 유전층의 조직 및 임피던스 분석 (Effects of Addition of Sulfuric Acid on the Etching Behavior of Al foil for Electrolytic Capacitors II. Microstructures of Dielectric Layers and AC Impedance Analysis)

  • 김성갑;유인종;신동철;오한준;지충수
    • 한국재료학회지
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    • 제10권5호
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    • pp.375-381
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    • 2000
  • 전해콘텐서용 알루미늄박을 ammonium adipate 용액을 이용하여 $65^{\circ}C$에서 10분간 100V 및 140V로 각각 양극 산화시켜 산화 알루미늄 유전체를 만들었다. 유전층의 두께, 화학양론적 관계, 결정구조 등을 RBS 및 TEM을 이용하여 분석하였고, 알루미늄박의 에칭시 황산 첨가로 인한 표면적의 변화는 임피던스 분석법으로 조사 하였다. 생성된 유전피막은 100V 및 140V의 전압을 사용했을 경우 각각 약 130nm 및 190nm 두께의 비정질로 나타났으며 피막의 알루미늄과 산소원소의 화학양자론적 비는 약 2:3의 비율로 존재했다. 또한 유전피막은 전자빔은 조사에 의해 쉽게 $${\gamma}$-Al_2$$O_3$ 형태의 결정질로 변태 되었다. 염산 에칭욕에 황산 첨가시 나타나는 알루미늄박의 표면변화는 임피던스 분석결과와 정전 용략의 변화가 일치하는 경향을 나타냈다.

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Engineered tunnel barrier가 적용되고 전화포획층으로 $HfO_2$를 가진 비휘발성 메모리 소자의 특성 향상 (Enhancement of nonvolatile memory of performance using CRESTED tunneling barrier and high-k charge trap/bloking oxide layers)

  • 박군호;유희욱;오세만;김민수;정종완;이영희;정홍배;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.415-416
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    • 2009
  • The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

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Quantitative Analysis of Ultrathin SiO2 Interfacial Layer by AES Depth Profilitng

  • Soh, Ju-Won;Kim, Jong-Seok;Lee, Won-Jong
    • The Korean Journal of Ceramics
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    • 제1권1호
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    • pp.7-12
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    • 1995
  • When a $Ta_O_5$ dielectric film is deposited on a bare silicon, the growth of $SiO_2$ at the $Ta_O_5$/Si interface cannot be avoided. Even though the $SiO_2$ layer is ultrathin (a few nm), it has great effects on the electrical properties of the capacitor. The concentration depth profiles of the ultrathin interfacial $SiO_2$ and $SiO_2/Si_3N_4$ layers were obtained using an Auger electron spectroscopy (AES) equipped with a cylindrical mirror analyzer (CMA). These AES depth profiles were quantitatively analyzed by comparing with the theoretical depth profiles which were obtained by considering the inelastic mean free path of Auger electrons and the angular acceptance function of CMA. The direct measurement of the interfacial layer thicknesses by using a high resolution cross-sectional TEM confirmed the accuracy of the AES depth analysis. The $SiO_2/Si_3N_4$ double layers, which were not distinguishable from each other under the TEM observation, could be effectively analyzed by the AES depth profiling technique.

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High Performance Wilkinson Power Divider Using Integrated Passive Technology on SI-GaAs Substrate

  • Wang, Cong;Qian, Cheng;Li, De-Zhong;Huang, Wen-Cheng;Kim, Nam-Young
    • Journal of electromagnetic engineering and science
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    • 제8권3호
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    • pp.129-133
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    • 2008
  • An integrated passive device(IPD) technology by semi-insulating(SI)-GaAs-based fabrication has been developed to meet the ever increasing needs of size and cost reduction in wireless applications. This technology includes reliable NiCr thin film resistor, thick plated Cu/Au metal process to reduce resistive loss, high breakdown voltage metal-insulator-metal(MIM) capacitor due to a thinner dielectric thickness, lowest parasitic effect by multi air-bridged metal layers, air-bridges for inductor underpass and capacitor pick-up, and low chip cost by only 6 process layers. This paper presents the Wilkinson power divider with excellent performance for digital cellular system(DCS). The insertion loss of this power divider is - 0.43 dB and the port isolation greater than - 22 dB over the entire band. Return loss in input and output ports are - 23.4 dB and - 25.4 dB, respectively. The Wilkinson power divider based on SI-GaAs substrates is designed within die size of $1.42\;mm^2$.

The influence of the initial stresses on Lamb wave dispersion in pre-stressed PZT/Metal/PZT sandwich plates

  • Kurt, Ilkay;Akbarov, Surkay D.;Sezer, Semih
    • Structural Engineering and Mechanics
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    • 제58권2호
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    • pp.347-378
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    • 2016
  • Within the scope of the plane-strain state, by utilizing the three-dimensional linearized theory of elastic waves in initially stressed piezoelectric and elastic materials, Lamb wave propagation and the influence of the initial stresses on this propagation in a sandwich plate with pre-stressed piezoelectric face and pre-stressed metal elastic core layers are investigated. Dispersion equations are derived for the extensional and flexural Lamb waves and, as a result of numerical solution to these equations, the corresponding dispersion curves for the first (fundamental) and second modes are constructed. Concrete numerical results are obtained for the cases where the face layers' materials are PZT-2 or PZT-6B, but the material of the middle layer is Steel (St) or Aluminum (Al). Sandwich plates PZT-2/St/PZT-2, PZT-2/Al/PZT-2, PZT-6B/St/PZT-6B and PZT-6B/Al/PZT-6B are examined and the influence of the problem parameters such as piezoelectric and dielectric constants, layer thickness ratios and third order elastic constants of the St and Al on the effects of the initial stresses on the wave propagation velocity is studied.

Sr$_2AlTaO_6$ 절연막을 이용한 계면처리된 경사형 모서리 조셉슨 접합의 제작 (Fabrication of the interface-treated ramp-edge Josephson junctions using Sr$_2AlTaO_6$ insulating layers)

  • 최치홍;성건용;한석길;서정대;강광용
    • 한국초전도학회:학술대회논문집
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    • 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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    • pp.63-66
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    • 1999
  • We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. Low-dielectric Sr$_2AITaO_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2Cu_3O_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the bottom YBCO edge using plasma treatment prior to deposition of the top YBCO electrode. We investigated the effects of pre-annealing and post-annealing on the characteristics of the interface-treated Josephson junctions. The junction parameters were improved by using in-situ RF plasma cleaning treatment.

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