• Journal of the Korean Society for Precision Engineering
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• v.17 no.2
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• pp.130-136
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• 2000

Generally, the build-up printed circuit board manufactured by the sequential process with etching, plating, drilling etc. requires many types of equipments and lead time. Etching process is suitable for mass production, however, it is not adequate for manufacturing prototype in the developing stage. In this study, we introduce a screen printing technology to prototyping a build-up printed circuit board. As for the material, photo/thermal curable resin and conductive paste are used for the formation of dielectric and conductor. The build-up structure is made by subsequent processes such as the formation of liquid resin thin layer, the solidification by UV/IR light, and via filling with conductive paste. By use of photo curable resin, productivity is greatly enhanced compared with thermal curable resin. Finally, the basic concept and the possibility of build-up printed circuit board prototyping are proposed in comparison with to the conventional process.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1509-1511
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• 2001

In this study, etching characteristics of polyimide(Pl) film with $O_2/CF_4$ gas mixing ratio was studied using inductively coupled plasma (ICP). The etch rate and selectivity were evaluated to chamber pressure and gas mixing ratio. High etch rate (over 8000$\AA$/min) and vertical profile were acquired in $CF_4$/($CF_4+O_2$) of 0.2. The selectivities of polyimide to PR and polyimide to $SiO_2$ were 1.15, 5.85, respectively. The profiles of polyimide film etched in $CF_4/O_2$ were measured by a scanning electron microscope (SEM) with using an aluminum hard mask pattern. The chemical states on the polyimide film surface were measured by x-ray photoelectron spectroscopy (XPS).

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.551-552
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• 2006

Plasma-induced charging damage was been measured during TaN gate electrode of MISFET(TaN/$HfO_2$/Si) or interconnection metal etching step using large antenna structures. The results of these experiments were obtained that $HfO_2$ gate dielectric layer was affected about plasma charging effects and damage increased with F-N tunneling. Therefore, the etching conditions should be optimized to avoid the defects caused by plasma charging.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.105-105
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• 2009

$ZrO_2$ is one of the most attractive high dielectric constant (high-k) materials. As integrated circuit device dimensions continue to be scaled down, high-k materials have been studied more to resolve the problems for replacing the EY31conventional $SiO_2$. $ZrO_2$ has many favorable properties as a high dielectric constant (k= 20~25), wide band gap (5~7 eV) as well as a close thermal expansion coefficient with Si that results in good thermal stability of the $ZrO_2/Si$ structure. In order to get fine-line patterns, plasma etching has been studied more in the fabrication of ultra large-scale integrated circuits. The relation between the etch characteristics of high-k dielectric materials and plasma properties is required to be studied more to match standard processing procedure with low damaged removal process. Due to the easy control of ion energy and flux, low ownership and simple structure of the inductively coupled plasma (ICP), we chose it for high-density plasma in our study. And the $BCl_3$ included in the gas due to the effective extraction of oxygen in the form of $BCl_xO_y$ compound In this study, the surface kinetic properties of $ZrO_2$ thin film was investigated in function of Ch addition to $BCl_3/Ar$ gas mixture ratio, RF power and DC-bias power based on substrate temperature. The figure 1 showed the etch rate of $ZrO_2$ thin film as function of gas mixing ratio of $Cl_2/BCl_3/Ar$ dependent on temperature. The chemical state of film was investigated using x-ray photoelectron spectroscopy (XPS). The characteristics of the plasma were estimated using optical emission spectroscopy (OES). Auger electron spectroscopy (AES) was used for elemental analysis of etched surface.

• Journal of Sensor Science and Technology
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• v.9 no.1
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• pp.9-14
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• 2000

Dielectric characteristics of P(VDF/TrFE) film manufactured using spin coating technique have been investigated. To improve the crystallinity and quality of film, the film was three step annealed. Simple etching process and conditions for P(VDF/TrFE) film were established using top electrode as a mask. Poling is performed by several steps. $1.87\;{\mu}m$ thick P(VDF/TrFE) films were obtained with conditions such that the solution of 10 wt% concentration was spun at 3000rpm for 30 seconds. Before poling, dielectric constant and dielectric loss of P(VDF/TrFE) film were 13.5 and 0.042, respectively. After poling, dielectric constant and dielectric loss of P(VDF/TrFE) film were 11.5 and 0.037, respectively.

• Journal of the Korean Vacuum Society
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• v.10 no.2
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• pp.252-256
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• 2001

We performed spectroscopic ellipsometry measurement to obtain dielectric function(DF) of ZnSe at room temperature. Proper wet chemical etching procedure was carried out to remove overlayers on top of ZnSe, and our result indicates that the previous reports on the pure DF of ZnSe have inaccurate interpretations. We constructed DF of oxide on ZnSe by using reported DFs of amorphous-Se, $GaAsO_3$, and voids through Bruggeman effective-medium approximation.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.130-137
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• 1995

Deopsition of thermal quality SiO2 using a high density plasma ECR CVD process has been demonstrated to give void and seam free gap fill of high aspect ratio metallization structures with a simple oxygen-silane chemistry. This is achieved by continuous sputter etching of the film during the deposition process. A two-step process is utilized to deposit a composite layer for higher manufacturing efficiency. The first step, which has a deposition rate of approximately 0.5 $\mu$m/min., is used to provide complete gap fill between the metal lines. The second step, which has a deposition rate of up to 1.5 $\mu$m/min., is used to deposit a total thickness of 2.0$\mu$m for the intermetal dielectric film. The topography of this composite film is very compatible with subsequent chemicl mechanical polishing(CMP) planarization processing.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.5
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• pp.680-687
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• 1999

An extensive study on miniaturized bandpass filter(BPF) appropriate for mobile communication systems is presented in this paper. The miniaturization has been accomplished by incorporating low-loss high-index materials inside a resonating cavity fabricated in silicon substrate using micromachining etching techniques. By use of materials with dielectric constant $\varepsilon_r$=500, filters with volume less than 0.11 $mm^3$ have been designed at the center frequency of 5.8 GHz with 3.3% bandwidth. The electrical performances and design tolerances of these filters for a variety of materials and shapes are discussed and design guidelines are presented herein.