• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.

• 한국진공학회지
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• 제6권3호
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• pp.220-226
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• 1997

실리콘 미세가공기술로 형성된 프레임 모양의 실리콘 기판에 의해 지지되는 -$Si_3N_4/300 nm-SiO_2/150 nm-Si_3N_4$ 광반사막을 제조하였으며, 이것을 광섬유와 결합하여 강도형 다모드 광섬유 압력센서를 제작하고 그 특성을 조사하였다. $Si_3N_4/SiO_2/Si_3N_4$다아아 프램을 광반사막으로 사용하기 위하여 이 다이아프램의 뒷면에 NiCr 및 Au 박막을 각각 진 공증착하여 광반사막에서의 광투과에 의한 광손실을 수%로 감소시킬 수 있었다. 유전체 다 이아프램의 상하에 각각 있는 $Si_3N_4$막은 KOH 수용액에 의한 실리콘 이방성 식각시 자동식 각 정지층 역할을 하여 다이아프램 두께의 재현성이 우수하였다. 다이아프램의 크기가 3$\times$ 3$\textrm{mm}^2$, 4$\times$4$\textrm{mm}^2$ 및 5$\times$5$\textrm{mm}^2$인 센서는 각각 0~126.64kPa, 0~79.98kPa 및 0~46.66kPa의 압력범위에서 선형적인 광출력-압력 특성을 나타내었으며, 이들 센서의 압력감도는 각각 약 20.69nW/kPa, 26.70nW/kPa 및 39.33nW/kPa로서, 다이아프램의 크기가 증가할수록 압력감 도도 증가하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 센서학회지
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• 제7권3호
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• pp.147-153
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• 1998

$Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$(N/O/N) 다이아프램과 결합된 고감도의 광섬유 Fabry-Peort 압력센서를 개발하여 스트레인 및 그 응답특성을 조사하였다. 먼저, 44 wt% KOH 수용액을 이용한 실리콘 이방성식각기술로 600 nm 두께의 N/O/N 다이아프램을 제조하였으며, 제조된 다이아프램과 광섬유 Fabry-Perot 간섭계를 결합하여 광섬유 압력센서를 구성하였다. 단일모드 광섬유(SMF)내에 $TiO_{2}$ 유전체 박막을 용융접합하여 공극의 길이가 약 2 cm인 광섬유 Fabry-Perot 간섭계를 제작하였다. 광섬유 Fabry-Perot 간섭계의 한쪽 끝은 N/O/N 다이아프램과 결합하였으며, 나머지 한쪽을 3 dB 광결합기를 통해 광측정장치에 연결하였다. $2{\times}2\;mm^{2}$ 및 $8{\times}8\;mm^{2}$ 크기의 N/O/N 다이아프램에 대해 응답특성을 조사한 결과, 각각 약 0.11 rad/kPa과 1.57 rad/kPa의 압력감도를 나타내었으며, 선형오차는 0.2 %FS이내였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.832-835
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• 2001

We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

• 한국정보통신학회논문지
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• 제4권2호
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• pp.297-305
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• 2000

본 논문에서는 다양한 안테나 면적을 가지는 다결정실리콘(poly-Si) 및 폴리사이드(polycide) 게이트 물질을 게이트로 갖는 커패시터 및 n/p-MOS 트랜지스터를 사용하여 AAR(Antenna Area Ratio)의 크기에 따른 플라즈마 피해를 측정 및 분석하였다. 플라즈마 공정에 대한 신뢰도 특성을 조사하기 위해, MOS 소자의 게이트 물질을 달리하여 플라즈마 공정에 대한 초기 특성 및 F-N 스트레스와 hot carrier 스트레스 인가시의 n/p-MOSFET의 열화 특성을 측정한 결과 금속 AR에 의하여 플라즈마 공정의 영향을 받는 것으로 관찰되었다. 폴리사이드 게이트 구조가 다결정실리콘 게이트 구조보다 AAR에 따른 정전류 스트레스 인가시의 TDDB(Time Dependent Dielectric Breakdown)및 게이트 전압의 변화 등과 같은 신뢰성 특성에서 상당히 개선됨을 알 수 있었다. 이는 텅스텐 폴리사이드 형성 공정 중에 불소가 게이트 산화막에 함유되었기 때문인 것으로 설명할 수 있으며, 게이트 물질로 폴리사이드를 사용한 소자에서 플라즈마 영향을 줄일 수 있다는 사실이 차세대 MOS 소자의 게이트 박막으로 폴리사이드 게이트 박막을 활용할 수 있는 가능성을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.863-866
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• 1999

(Ba,Sr)$TiO_3$ thin films have attracted groat interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2$/Ar plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage = 600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2, the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is 480$\AA/min$ at 10 % $BCl_3$ adding to $Cl_2$/Ar. The characteristics of the plasmas were estimated using optical emission spectroscopy (OES). The change of Cl, B radical density measured by OES as a function of $BCl_3$ percentage in $Cl_2$/Ar. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2$/Ar. To study on the surface reaction of (Ba,Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion enhancement etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and Tic14 is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about $65\;{\sim}\;70$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.523-523
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• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.210-210
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• 2011

The effects of CH2F2 and N2 gas flow rates on the etch selectivity of silicon nitride (Si3N4) layers to extreme ultra-violet (EUV) resist and the variation of the line edge roughness (LER) of the EUV resist and Si3N4 pattern were investigated during etching of a Si3N4/EUV resist structure in dual-frequency superimposed CH2F2/N2/Ar capacitive coupled plasmas (DFS-CCP). The flow rates of CH2F2 and N2 gases played a critical role in determining the process window for ultra-high etch selectivity of Si3N4/EUV resist due to disproportionate changes in the degree of polymerization on the Si3N4 and EUV resist surfaces. Increasing the CH2F2 flow rate resulted in a smaller steady state CHxFy thickness on the Si3N4 and, in turn, enhanced the Si3N4 etch rate due to enhanced SiF4 formation, while a CHxFy layer was deposited on the EUV resist surface protecting the resist under certain N2 flow conditions. The LER values of the etched resist tended to increase at higher CH2F2 flow rates compared to the lower CH2F2 flow rates that resulted from the increased degree of polymerization.

• 센서학회지
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• 제22권2호
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.