• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.142.2-142.2
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• 2015

Plasma etch endpoint detection (EPD) of SiO2 and PR layer is demonstrated by plasma impedance monitoring in this work. Plasma etching process is the core process for making fine pattern devices in semiconductor fabrication, and the etching endpoint detection is one of the essential FDC (Fault Detection and Classification) for yield management and mass production. In general, Optical emission spectrocopy (OES) has been used to detect endpoint because OES can be a simple, non-invasive and real-time plasma monitoring tool. In OES, the trend of a few sensitive wavelengths is traced. However, in case of small-open area etch endpoint detection (ex. contact etch), it is at the boundary of the detection limit because of weak signal intensities of reaction reactants and products. Furthemore, the various materials covering the wafer such as photoresist (PR), dielectric materials, and metals make the analysis of OES signals complicated. In this study, full spectra of optical emission signals were collected and the data were analyzed by a data-mining approach, modified K-means cluster analysis. The K-means cluster analysis is modified suitably to analyze a thousand of wavelength variables from OES. This technique can improve the sensitivity of EPD for small area oxide layer etching processes: about 1.0 % oxide area. This technique is expected to be applied to various plasma monitoring applications including fault detections as well as EPD.

• ETRI Journal
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• v.38 no.4
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• Korean Journal of Materials Research
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• v.10 no.5
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• pp.375-381
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• 2000

Aluminium foil for electrolytic capacitors was anodized at the voltage of 100V and 140V for 10 minutes in ammonium adipate solution to form aluminum oxide layer on aluminum substrate as an dielectric film. The thickness, the stoichiometry and the crystal structure of the layer were investigated by using RBS and TEM . In addition EIS technique was employed to study the effects of addition of sulfuric acid on the increment of the foil surface area. It was found that the thickness values of the layers anodized at 100V and 140V were about 130 nm and 190 nm respectively and the stoichiometry of the elements of aluminum and oxygen was 2:3. The anodic oxide layer was shown to be amorphous. but the structure irradiated with electron beam resulted in the transformation into crystalline structure of $${\gamma}$-Al_2$$O_3$ . From a comparison of the impedance results and the capacitance variation to investigate the ef- fects of sulfuric acid addition to the etching bath of hydrochloric acid, the EIS techinque could be useful to analyze the capacitance variation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.393-397
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• 2002

Polyimide (PI) films have been studied widely as the interlayer dielectric materials due to a low dielectric constant, low water absorption, high gap-fill and planarization capability. The polyimide film was etched using inductively coupled plasma system. The etcying characteristics such as etch rate and selectivity were evaluated at different $CF_4/(CF_4+O_2)$chemistry. The maximum etch rate was 8300 ${\AA}/min$ and the selectivity of polyimide to SiO$_2$was 5.9 at $CF_4/(CF_4+O_2)$ of 0.2. Etch profile of polyimide film with an aluminum pattern was measured by a scanning electron microscopy. The vertical profile was approximately $90^{\circ}$ at $CF_4/(CF_4+O_2)$ of 0.2. As 20% $CF_4$ were added into $O_2$ plasma from the results of the optical emission spectroscopy, the radical densities of fluorine and oxygen increased with increasing $CF_4$ concentration in $CF_4/O_2$ from 0 to 20%, resulting in the increased etch rate. The surface reaction of etched PI films was investigated using x-ray photoelectron spectroscopy.

• Journal of Korean Society for Atmospheric Environment
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• v.20 no.5
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• pp.625-632
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• 2004

Perfluorocompounds ($PFC_s$), such as tetrafluoromethane ($CF_4$) and hexafluoroethane ($C_2F_6$), have been widely used as plasma etching and chemical vapor deposition (CVD) gases for semiconductor manufacturing processes. Since these $PFC_s$ are known to cause a greenhouse effect intensively, there has been a growing interest in reducing $PFC_s$ emissions. Among various $CF_4$ decomposing techniques, a dielectric barrier discharge (DBD) is considered as one of a promising candidate because it has been successfully used for generating ozone ($O_3$) and decomposing nitrogen oxide (NO). Firstly, optimal concentration of oxygen for $CF_4$ decomposition was found to figure out how many primary and secondary reactions are associated with DBD process. Secondary, to find effective discharge method for $CF_4$ decomposition, a streamer and a glow mode in DBD are experimentally compared, which includes (i) coaxialcylinder DBD, (ii) DBD reactor packed with glass beads. and (iii) a glow mode operation with a helium gas. The test results showed that optimal concentration of oxygen was ranged 500 ppm~1% for treating 500 ppm of $CF_4$ and helium glow discharge was the most efficient one to decompose $CF_4$.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• Journal of the Speleological Society of Korea
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• no.76
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• pp.37-42
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• 2006

The Dielectric Barrier Discharge (DBD) is a nonequilibrium gas discharge that is generated in the space between two electrodes, which are separated by an insulating dielectric layer. The dielectric layer can be put on either of the two electrodes or be inserted in the space between two electrodes. If an AC or pulse high voltage is applied to the electrodes that is operated at applied frequency from 50Hz to several MHz and applied voltages from a few to a few tens of kilovolts rms, the breakdown can occur in working gas, resulting in large numbers of micro-discharges across the gap, the gas discharge is the so called DBD. Compared with most other means for nonequilibrium discharges, the main advantage of the DBD is that active species for chemical reaction can be produced at low temperature and atmospheric pressure without the vacuum set up, it also presents many unique physical and chemical process including light, heat, sound and electricity. This has led to a number of important applications such as ozone synthesizing, UV lamp house, CO2 lasers, et al. In recent years, due to its potential applications in plasma chemistry, semiconductor etching, pollution control, nanometer material and large area flat plasma display panels, DBD has received intensive attention from many researchers and is becoming a hot topic in the field of non-thermal plasma.

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.103-108
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• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• Journal of Integrative Natural Science
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• v.2 no.1
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• pp.45-49
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• 2009

Electrochemical etching of heavily doped p-type silicon wafers (boron doped, <100> orientation, resistivity; $0.8-1.2m{\Omega}/cm$) with different current density resulting two different refractive indices resulted in DBR (Distributed Bragg Reflectors) porous silicon, which exhibited strong in-plane anisotropy of refractive index (birefringence). Dielectric stacks of birefringent porous silicon acting as distributed Bragg reflectors have two distinct reflection bands depending on the polarization of the incident linearly polarized light. This effect is caused by a three-dimensional (in plane and in depth) variation of the refraction index. Optical characteristics of DBR porous silicon were investigated.