• Title/Summary/Keyword: Dickson charge pump

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Design of Voltage Multiplier based on Charge Pump using Modified Voltage Doubler Circuit (배전압 회로를 적용한 변형된 Charge Pump 기반 전압 증배기 설계)

  • Yeo, Hyeop-Goo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.8
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    • pp.1741-1746
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    • 2012
  • This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generates about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

Dickson Charge Pump with Gate Drive Enhancement and Area Saving

  • Lin, Hesheng;Chan, Wing Chun;Lee, Wai Kwong;Chen, Zhirong;Zhang, Min
    • Journal of Power Electronics
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    • v.16 no.3
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    • pp.1209-1217
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    • 2016
  • This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

Design of a Voltage Multipler Circuit using a Modified Voltage Doubler (개선된 배전압 회로를 이용한 전압증배기 회로 설계)

  • Yeo, Hyeop-Goo;Jung, Seung-Min;Sonh, Seung-Il;Kang, Min-Koo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.696-698
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    • 2012
  • This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generate about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

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A New Capacitive Sensing Circuit using Modified Charge Transfer Scheme

  • Yeo, Hyeop-Goo
    • Journal of information and communication convergence engineering
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    • v.9 no.1
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    • pp.78-82
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    • 2011
  • This paper proposes a new circuit for capacitive sensing based on Dickson's charge pump. The proposed touch sensing circuit includes three stages of NMOS diodes and capacitors for charge transfer. The proposed circuit which has a simplified capacitive touch sensor model has been analyzed and simulated by Spectre using Magna EDMOS technology. Looking from the simulation results, the proposed circuit can effectively be used as a capacitive touch sensing circuit. Moreover, a simple structure can provide maximum flexibility for making a digitally-controlled touch sensor driver with lowpower operations.

A Multi-Stage CMOS Charge Pump for Low-Voltage Memories

  • Lim, Gyu-Ho;Yoo, Sung-Han;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.05a
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    • pp.283-287
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    • 2002
  • To remedy both the degradation and saturation of the output voltages in the modified Dickson pump. a new multi-stage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94 even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

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Design of a Low-Power and Low-Area EEPROM IP of 256 Bits for an UHF RFID Tag Chip (UHF RFID 태그 칩용 저전력, 저면적 256b EEPROM IP 설계)

  • Kang, Min-Cheol;Lee, Jae-Hyung;Kim, Tae-Hoon;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.671-674
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    • 2009
  • We design a low-power and low-area asynchronous EEPROM of 256 bits used in a passive UHF RFID tag chip. For a low-power solution, we use a supply voltage of 1.8V and design a Dickson charge pump using N-type Schottky diodes with a low-voltage characteristic. And we use an asynchronous interface and a separate I/O method for a low-area solution of the peripheral circuit of the designed EEPROM. And we design a Dickson charge pump using N-type Schottky diodes to reduce an area of DC-DC converter. The layout area of the designed EEPROM of 256 bits with an array of 16 rows and 16 columns using $0.18{\mu}m$ EEPROM process is $311.66{\times}490.59{\mu}m^2$.

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A design on low-power and small-area EEPROM for UHF RFID tag chips (UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계)

  • Baek, Seung-Myun;Lee, Jae-Hyung;Song, Sung-Young;Kim, Jong-Hee;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2366-2373
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    • 2007
  • In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

A Multi-Stage CMOS Charge Pump for Low-Voltage Memories

  • Kim, Young-Hee;Lim, Gyu-Ho;Yoo, Sung-Han;Park, Mu-Hun;Ko, Bong-Jin;Cho, Seong-Ik;Min, Kyeong-Sik;Ahn, Jin-Hong;Chung, Jin-Yong
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.369-372
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    • 2002
  • To remedy both the degradation and saturation of the output voltages in the modified Dickson pump, a new multistage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94V even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

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A New Analog Switch CMOS Charge Pump Circuit without Body Effect

  • Parnklang, Jirawath;Manusphrom, Ampual;Laowanichpong, Nut;Tongnoi, Narongchai
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.212-214
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    • 2005
  • The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

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High-speed charge pump circuits using weighted-capacitor and multi-path (Weighted-capacitor와 multi-path를 이용한 고속 승압 회로)

  • 김동환;오원석;권덕기;이광엽;박종태;유종근
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.863-866
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    • 1998
  • In this paper two quick boosting charge pump circuits for high-speed EEPROM memory are proposed. In order to improve initial charge transfer efficiency, one uses weighted capacitors where each stage has different clock coupling capacitance, and the other uses a multi-path structure at the first stage. SPICE simulation results show that these charge pumps have improve drising-time characteristics, but their $V_{DD}$ mean currents are increased a little compared with conventioanl charge pumps. The rising time upt o 15V of the proposed charge pumps is 3 times faster than that of dickson's pump at the cost of 1.5 tiems more $V_{DD}$ mean current.rrent.

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