• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.179.1-179.1
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• 2007

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.213-225
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• 2002

Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.165-172
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• 2024

In this study, we investigated the detection properties of piezoresistive carbon nanotubes/polydimethylsiloxane (CNT/PDMS) devices with porous structures under applied pressure. The device, having dimensions of 10 mm × 10 mm × 5 mm, was fabricated with a porosity of 74.5%. To fabricate piezoresistive CNT/PDMS devices, CNTs were added using two different methods. In the first method, the CNTs were mixed with PDMS before the fabrication of the porous structure, while in the second, the CNTs were coated after the fabrication of the porous structure. Various detection properties of the fabricated devices were examined at different applied pressures. The CNT-coated device exhibited stable outputs with lesser variation than the CNT-mixed device. Moreover, the CNT-coated device exhibited improved reaction properties. The response time of the CNT-coated device was 1 min, which was approximately about 20 times faster than that of the CNT-mixed device. Considering these properties, CNT-coated devices are more suitable for sensing devices. To verify the CNT-coated device as a real sensor, it was applied to the gripping sensor system. A multichannel sensor system was used to measure the pressure distribution of the gripping sensor system. Under various gripping conditions, this system successfully measured the distributed pressures and exhibited stable dynamic responses.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.94.4-94
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• 1998

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.8
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• pp.869-874
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• 2014

It is possible to fabricate a three-dimensional (3D) shape using the solid freeform fabrication (SFF) technology. However, there are several problems in applying conventional SFF technologies to the direct manufacturing of a product. Hence, multimaterial SFF is gaining attention. Moreover, a 3D circuit device that is different from a conventional two-dimensional PCB can also be fabricated using multimaterial SFF. In this study, a hybrid system using fused deposition modeling and direct writing was designed for 3D circuit device fabrication.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.30-37
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• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control'writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm). To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and 0.5 $\times$ 0.5 mm$^2$area, respectively. This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.8
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• pp.577-579
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• 1999

DLC film remaining on device surface could be removed by eliminating AI sacrificial layer as a final step of lift-off process in the fabrication of DLC-coated Si-tip FEA. The field emission properties(I-V curves, hysteresis, and current fluctuation etc.) of the processed device were analyzed and the process was employed to 1.76 inch-sized FEA panel fabrication in order to evaluate its FED applicability.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.6
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• pp.16-19
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• 1976

InSb-Sn thin film Hall device Was drepared by flash evaporation of InSb-Sn powder on the Slide qlass. The Characteristics Curve of this device showcd good linearity and reproducibility.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.80-80
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• 2006

As the size scale of features continue to shrink in devices, the use of self-assembly, i.e. a "bottom up" approach, for device fabrication becomes increasingly important. Yet, simple self-assembly alone will not be sufficient to meet the increasing demands place on the registry of structures, particularly nanostructured materials. Several criteria are key in the rapid advancement and technology transfer for self-assembling systems. Specifically, the assembly processes must be compatible with current $^{\circ}{\infty}top\;down^{\circ}{\pm}$ approaches, where standard photolithographic processes are used for device fabrication. Secondly, simple routes must be available to induce long-range order, in either two or three dimensions, in a rapid, robust and reliable manner. Thirdly, the in-plane orientation and, therefore, ordering of the structures, must be susceptible to a biasing by an external, macroscopic means in at least one, if not two directions, so that individual elements can be accessed in a reliable manner. Block copolymers, specifically block copolymers having a cylindrical microdomain morphology, are one such material that satisfy many, if not all, of the criteria that will be necessary for device fabrication. Here, we discuss several routes by which these versatile materials can be used to produce arrays of nanoscopic elements that have high aspect ratios (ideal for templating and scaffolding), that exhibit long-range order, that give access to multiple length scale structuring, and that are amenable to being biased by macroscopic features placed on a surface.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.902-909
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• 1991

A reproducible selective dry etch process of GaAs/AlGaAs Heterostructures for High Electron Mobility Transistor(HEMT) Device fabrication is developed. Using RIE mode with $CCl_{2}F_{2}$ as the basic process gas, the observed etch selectivity of GaAs layer with respect to GaAs/$Al_{0.3}Ga_{0.7}$As is about 610:1. Severe polymer deposition problem, parialy generated from the use of $CCl_{2}F_{2}$ gas only, has been significantly reduced by adding a small amount of He gas or by $O_{2}$ plasma ashing after etch process. In order to obtain an optimized etch process for HEMT device fabrication, we com pared the properties of the wet etched Schottky contact with those of the dry etched one, and set dry etch condition to approach the characteristics of Schottky diode on wet etched surface. By applying the optimized etch process, the fabricated HEMT devices have the maximum transconductance $g_{mext}$ of 224 mS/mm, and have relatively uniform distribution across the 2inch wafer in the value of 200$\pm$20mS/mm.