• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.505-508
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• 2006

Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.131-132
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• 2005

In this paper, the capacitance properties of degraded thyristor with temperature and voltage were presented. As degraded thyristor, 8 thyristors with each other different reverse blocking voltage used. Its impedance and resistance properties were measured from frequency 100Hz to 10MHz applied with bias voltage from 0V to 40V. As a result, at low frequency region, that is, at the frequency 100 - 10kHz, the abrupt increasement of its capacitance was confirmed. And also, at high frequency region, the capacitance peak move toward low frequency in the region of frequency 4 - 6MHz as degradation of thyristor.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.413-413
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• 2012

Lead sulfide (PbS) Colloidal quantum dots (CQDs) are promising material for the photovoltaic device due to its various outstanding properties such as tunable band-gap, solution processability, and infrared absorption. More importantly, PbS CQDs have large exciton Bohr radius of 20 nm due to the uniquely large dielectric constants that result in the strong quantum confinement. To exploit desirable properties in photovoltaic device, it is essential to fabricate a device exhibiting stable performance. Unfortunately, the performance of PbS NQDs based Schottky solar cell is considerably degraded according to the exposure in the air. The air-exposed degradation originates on the oxidation of interface between PbS NQDS layer and metal electrode. Therefore, it is necessary to enhance the stability of Schottky junction device by inserting a passivation layer. We investigate the effect of insertion of passivation layer on the performance of Schottky junction solar cells using PbS NQDs with band-gap of 1.3 eV. Schottky solar cell is the simple photovoltaic device with junction between semiconducting layer and metal electrode which a significant built-in-potential is established due to the workfunction difference between two materials. Although the device without passivation layer significantly degraded in several hours, considerable enhancement of stability can be obtained by inserting the very thin LiF layer (<1 nm) as a passivation layer. In this study, LiF layer is inserted between PbS NQDs layer and metal as an interface passivation layer. From the results, we can conclude that employment of very thin LiF layer is effective to enhance the stability of Schottky junction solar cells. We believe that this passivation layer is applicable not only to the PbS NQDs based solar cell, but also the various NQDs materials in order to enhance the stability of the device.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.136-144
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• 2004

From the AC analysis results utilizing a two dimensional device simulator, the ac equivalent-circuit modeling of the ESD protection devices is executed. It is explained that the ac equivalent circuit of the NMOS protection transistor is modeled by a rather complicated form and that, depending on the frequency range, the error can be large if it is modeled by a simple RC serial circuit. It is also shown that the ac equivalent circuit of the thyristor-type pnpn protection device can be modeled by a simple RC serial circuit. Based on the circuit simulations utilizing the extracted equivalent circuits, the effects of the parasitics in the protection device on the characteristics of LNA are examined when the LNA, which is one of the important RF circuits, is equipped with the protection device. It is explained that a large error can result in estimating the circuit characteristics if the NMOS protection transistor is modeled by a simple capacitor. It is also confirmed that the degradation of the LNA characteristics by incorporating the ESD protection device can be reduced a lot by adopting the suggested pnpn device.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.11
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• pp.490-492
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• 2005

A study on radiation hardening of infrared(IR) detector, the chief component of IR camera was performed. The radiation test on IR sensor passivated with the ZnS by Co$^{60}$ gamma-ray over 1 Mrads showed the reduction in Ro by 1/100 which was related to the noise level. This effect that was caused by carrier trapping in the ZnS passivation layer increased the leakage current and resulted in degradation in the device performance. For the radiation hardening of IR devices we suggested the ones with CdTe passivation layer which had a tendency to reluctant to carrier trapping in its layer and developed test patterns. Radiation test to the patterns showed that the our CdTe passivated device could survived over 1 Mrad gamma-ray dose.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.347-353
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• 2017

We present a STT-MRAM read-circuit which mitigates the performance degradation caused by offsets from device mismatches. In the circuit, a single current source supplies read-current to both the data and the reference cells sequentially eliminating potential mismatches. Furthermore, an offset-free pre-amplification using a capacitor storing the mismatch information is employed to lessen the effect of the comparator offset. The proposed circuit was implemented using a 130-nm CMOS technology and Monte Carlo simulations of the circuit demonstrate its effectiveness in suppressing the effect of device mismatch.

• Proceedings of the KSRS Conference
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• 2005.10a
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• pp.601-603
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• 2005

Refocusing methods are used to compensate optical performance degradation of high resolution satellite camera during on-orbit operation. Due to mechanical vibration during launch and thermal vacuum environment of space where camera is exposed, the alignment of optical system may have error. The focusing error is dominant of misalignment and caused by the de-space error of secondary mirror of catoptric camera, which is most sensitive to vibration and space environment. The high resolution camera of SPOT, Pleiades and KOMPSAT2 have refocusing device to adjust focusing during orbital operation while QuickBird of US does not use on orbit refocusing method. For the Korsch type optical configuration which is preferred for large aperture space remote sensing camera, secondary mirror and folding mirror are available as refocusing element.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.550-553
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• 2001

In this study, unity current gain frequency f$\_$T/ of GaAs MESFET is predicted with different temperatures up to 400 $^{\circ}C$. Temperature dependence parameters of the device including intrinsic carrier concentration n$\_$i/ effective mass, depletion width are considered to be temperature dependent. Small signal parameters such as gate-source, gate dran capacitances C$\_$gs/ C$\_$gd/ are correlated with transconductance g$\_$m/ to predict the unity current gain frequency. The extrinsic capacitance which plays an important roles in high frequency region has been taken into consideration in evaluating total capacitance by using elliptic integral through the substrate. From the results, f$\_$T/ decreases as the temperature increases due to the increase of small signal capacitances and the mobility degradation. Finally the extrinsic elements of capacitances have been proved to be critical in deciding f$\_$T/ which are originated from the design rule of the device.