• Journal of the Korean Society for Precision Engineering
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• v.21 no.10
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• pp.94-101
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• 2004

This paper presents the development of a keypad test system for the improvement of working environment and productivity using PTC 16F877 microprocessor. In order to detect the fault of keypad products, hardware and software design is performed in this system. Keypad fault detection system is controlled by the 8 bit one chip PIC microcontroller for the exactness and speed. Developed panel of the keypad test system is comprised of the sub-panel for selecting in the inspected keypad types and the main panel f3r displaying the working order and fault position. Furthermore, all data from keypad inspection are stored in main memory of personal computer for the database. All these functions lead to the improvement of working speed and environment.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.9
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• pp.915-919
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• 2007

This paper proposed a transponder detection method to reduce recognition time in RFID system. It's also shown that conventional procedure of communication in the system could cause a waste of time when a reader recognizes a transponder. The reduction of recognition time can be obtained by developing a circuit to detect a transponder actively. Detecting a transponder is achieved by using the voltage variation of reader antenna voltage that happens when a transponder approaches to the vicinity of magnetic field formed by the reader. By adding a comparator to the antenna receiver of a reader, the reader can perceive approach or existence of a transponder. A reader for experiment is made using the MFRC500 by Phillips that supports ISO/IEC 14443 protocol. Comparing the proposed method with the conventional methods by experiment, there are 47.5ms reduction of recognition time maximally and 12ms in average.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.66-76
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• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

• ETRI Journal
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• v.23 no.2
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• pp.77-84
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• 2001

The detection of open defects in CMOS SRAM has been a time consuming process. This paper proposes a new dynamic power supply current testing method to detect open defects in CMOS SRAM cells. By monitoring a dynamic current pulse during a transition write operation or a read operation, open defects can be detected. In order to measure the dynamic power supply current pulse, a current monitoring circuit with low hardware overhead is developed. Using the sensor, the new testing method does not require any additional test sequence. The results show that the new test method is very efficient compared with other testing methods. Therefore, the new testing method is very attractive.

• Proceedings of the KSR Conference
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• 2007.05a
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• pp.1650-1655
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• 2007

A lights-out detector, which helps the person in charge of maintenance make a quick judgment in the event of a failure of LED-type traffic lights, was explored/developed and installed/ tested, at Seoul Metro, after they developed a patented pilot product in 2005; and, a product improvement test was conducted to ensure reasonable maintenance of signaling facilities. Having better compatibility with existing circuit in use and displaying stable load current, the device makes the maintenance of lights-out detection and alert easier.

• Journal of Sensor Science and Technology
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• v.23 no.1
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• pp.24-28
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• 2014

A lock-in amplifier was proposed for capacitive sensor applications. This amplifier was based on a general-purpose microcontroller and had only a charge amplifier as analog circuits. All the other functions of lock-in amplifier except for the charge amplifier were implemented with firmware and the internal resources of the microcontroller. A rectangular signal, generated by the microcontroller, was used in a sensor-driving signal instead of a conventional sinusoidal signal. This makes it possible that the phase comparison circuit in the lockin amplifier is made with analog-to-digital converter, a timer and an interrupt controller. Using the oversampling method and the rectangular driving signal, we can make it easy to implement the peak detection function with software and sample the peak-to-peak signal at charge amplifier output. A charge amplifier was proposed to cancel out the base capacitance existing in capacitive sensors structurally. The experimental results show that the lock-in amplifier operating in the supply voltage of 3.0 V cancels out the base capacitance and has good linearity.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.312-315
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• 1995

The base/gate drive suppression method proposed by Joshi and Bose is that which detects the output current polarity of the leg and, according to the polarity, suppresses the base/gate drive of one of the ore switching devices of the leg. This method has the merit that it does not have the conventional dead time problem, reduces the power loss of the driving circuit and others. But this method has difficulty in implementation. In this paper, a new base/gate drive suppression method by detecting not the output current polarity but the output voltage polarity is proposed. The proposed method is easier to implement than Joshi and Bose's method.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.900-901
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• 2008

본 논문은 NPC 인버터(Neutral-point-clamped Inverter) 시스템을 구성하는 스위칭 소자에 개방성 고장이 발생하였을 경우 인버터 시스템의 고장 검출을 위한 새로운 고장 검출 방법을 제안하였다. 이 방법은 CPWM(continuous-PWM) 고유의 특성을 이용하기 때문에 간단한 알고리즘으로서 구현이 용이할 뿐만 아니라 기존의 방법보다 빠른 고장 검출 능력을 가진다. 빠른 고장 검출 능력은 고장 검출 시간의 지연에서 올 수 있는 직류-링크 커패시터의 전압 불평형 문제 및 이로 인한 다른 스위치로의 전압 스트레스 증가에 의한 소자 파괴와 같은 악영향을 개선시킬 수 있다. 제안된 방법의 타당성을 입증하기 위하여 실험을 수행하였다.