• Korean Journal of Computational Design and Engineering
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• v.2 no.4
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• pp.267-275
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• 1997

A ship-block cutting module is being developed as part of a computational system for a ship design. The module supports product-information to other modules in design process and displays ship-blocks in cutting-operation. Welding-information is essential to process-planning and scheduling. In the module, ship-blocks are modeled by Plate-Objects and then divided into several cutting pieces. The module automatically creates Welding-Objects containing welding-information in the process. Since the module is connected to WWW(World Wide Web), users in various platforms can access the models simultaneously In addition, users can check manufacturing constraints by inspecting a virtual model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

• Proceedings of the Korean Geotechical Society Conference
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• 2005.10a
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• pp.669-680
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• 2005

It is very difficult to determine the failure block scale in great rock slopes. Especially, postulating entire slope domain as a failure block without attention to discontinuity trace lenth makes very confuse and difficult to design rock slopes. In this paper, we estimate realistic failure block scale using joint system simulation method and introduce the application procedures on rock slope analysis. Besides, presenting how joint characteristics measurement and statistical analysis results are applicated to slope stability analysis design flow.

• Journal of applied mathematics & informatics
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• v.14 no.1_2
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• pp.343-351
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• 2004

In order to maintain load balancing in a distributed system, we should obtain workload information from all the nodes on network. This processing requires $O(v^2)$ communication overhead, where v is the number of nodes. In this paper, we present a new synchronous dynamic distributed load balancing algorithm on a (v, k ＋ 1, 1)-configured network applying a symmetric balanced incomplete block design, where $v\;=\;k^2$\;＋\;k\;＋\;1$. Our algorithm needs only $O(\sqrt[v]{v})$ communication overhead and each node receives workload information from all the nodes without redundancy. Therefore, load balancing is maintained since every link has the same amount of traffic for transferring workload information.

• Communications for Statistical Applications and Methods
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• v.6 no.1
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• pp.159-168
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• 1999

We introduce a new conditional signed-rank test for the tree alternatives comparing several treatments with a control in the randomized block design. We demonstrate its performance by comparing with 3 classes of signed-rank tests proposed by Park et al.(1991) in some general situations. In most cases the proposed procedure is simpler to compute and has better power than others.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.721-724
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• 2006

This paper presents a method of the constructing the digital logic switching functions and realizing the circuit design using partition techniques. First of all, we introduce the necessity, background and concepts of the partition design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the building block, based on each partition functions. And we apply the proposed method to the example, and we compare the results with the results of the earlier methods. In result, we describe the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1393-1399
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• 1999

In this paper, a VLSI design of the convolutional codec chip of code rate r=l/3, and constraint length K=9 is presented, which is able to correct errors of the received data when transmitted data is corrupted in channels. The circuit design mainly aimed for simple implementation. In the decoder, Viterbi algorithm with 3-bit soft-decision is employed. For information sequence updating and storage, the register exchange method is employed, where the register length is 5$\times$K(45 stages). The codec chip is designed using VHDL language and Design Analyzer and VHDL Simulator of Synopsys are used for simulation and synthesis. The chip is composed of ENCODER block, ALIGN block, BMC block, ACS block, SEL_MIN block and REG_EXCH block. The operation of the codec chip is verified though the logic simulations, where several error conditions are assumed. As a result of the timing simulation after synthesis, the decoding speed of 325.5Kbps is achieved, and 6,894 gates is used.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.6
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• pp.377-384
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• 2022

In the design of composite aircraft structures, it is very important to set material allowables and design values, which take into account certification. And when determining the material allowable and design value of composite structures, the static strength, damage tolerance requirements, and environmental effects should be considered. The building block approach has been applied to the civil and military aviation industry for a long time and provides the principal certification methodology. This current certification methodology is based on extensive testing including coupon, element, sub-component, and full scale test. In this paper, some examples of composite allowable tests have been presented and the fundamental background and application methods of the building block approach have been presented.

• Journal of Korean Tunnelling and Underground Space Association
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• v.12 no.3
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• pp.275-283
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• 2010

Recently, the observational design and construction method in tunnels has been becoming important. Rock masses include various discontinuities such as joints, faults, fractures, bedding planes, and, cracks. The behavior of tunnels in hard rocks, therefore, is generally controlled by various discontinuities. In this study, a new key block analysis method for observational design and construction method in tunnels is proposed, and then applied to the actual tunnel with a super-large cross-section. The proposed analysis method considers finite persistence of discontinuities. The new analysis method can handle concave and convex shaped blocks. To demonstrate the applicability of this key block analysis method for observational design and construction method in tunnels, the analysis results are examined and compared with those of the conventional method.