• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.151-156
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• 2016

The IoT technology and sensors used for collecting the environment information has rapidly increased the number and type. With the increasing need for this type of sensor effective system for selecting and testing the sensor nodes for the IoT to develop products and services. In this study, we design and implement IoT sensor testing system for IoT service and product. In order to support rapid prototyping, the proposed system provides testing and management tools for IoT sensor nodes. We analyze the requirements of the proposed system and design the system based on the functional component-specific design. Finally, we implement testing application to verify the functional elements of the proposed system.

• Journal of KIISE:Information Networking
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• v.28 no.3
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• pp.297-308
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• 2001

In this paper, we design, validate and implement WTP(Wireless Transaction Protocol) using SDT(SDL Design Tool). We do modeling WTP protocol by SDL(Specification and Description Language), design and implement the environment function for the interface between the SDL system and the UDP platform and design APIs(Application Programming Interface). And we do conformance testing for WTP protocol software using ITEX(Interactive TTCN Editor and eXecutor). We write ATS(Abstract Test Suite) by TTCN(Tree and Tabular Combined Notation) and make ETS(Executable Test Suite) by the TTCN compiler supplied by ITEX.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.378-390
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• 2006

Many distributed applications build overlays on top of the Internet. Several unsolved issues at the network layer can explain this trend to implement network services such as multicast, mobility, and security at the application layer. On one hand, overlays creating basic topologies are usually limited in flexibility and scalability. On the other hand, overlays creating complex topologies require some form of application level addressing, routing, and naming mechanisms. Our aim is to design an efficient and robust addressing, routing, and naming infrastructure for these complex overlays. Our only assumption is that they are deployed over the Internet topology. Applications that use our middleware will be relieved from managing their own overlay topologies. Our infrastructure is based on the separation of the naming and the addressing planes and provides a convergence plane for the current heterogeneous Internet environment. To implement this property, we have designed a scalable distributed k-resilient name to address binding system. This paper describes the design of our overlay infrastructure and presents performance results concerning its routing scalability, its path inflation efficiency and its resilience to network dynamics.

• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.21-27
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• 2008

In this paper, we design and implement the upstream packet bandwidth allocation algorithm on OPNET-based DOCSIS 3.0 simulator including channel-bonding CM (Cable Modem)s. Previous DOCSIS CM could not support channel bonding, it has problem in upstream bandwidth allocation and determine the contention area. The proposed upstream bandwidth allocation algorithm has been improved the queuing time and success rate. For the simulation, we design the MAC frame structure with channel bonding supported CM and not. And then, this paper design and implement the CMTS node model, CM node model, CMTS process model, and CM process model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1488-1494
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• 2008

This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• Journal of Communications and Networks
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• v.4 no.2
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• pp.81-89
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• 2002

In this paper, we design and implement an efficient fair off-line electronic cash system based on Elliptic Curve Discrete Logarithm Problem (ECDLP), in which the anonymity of coins is revocable by a trustee in case of dispute. To achieve this, we employ the Petersen and Poupard s electronic cash system [1] and extend it by using an elliptic curve over the finite field GF($2^n$). This naturally reduces message size by 85% compared with the original scheme and makes a smart card to store coins easily. Furthermore, we use the Baek et al. s provably secure public key encryption scheme [2] to improve the security of electronic cash system. As an extension, we propose a method to add atomicity into new electronic cash system. To the best of our knowledge, this is the first result to implement a fair off-line electronic cash system based on ECDLP with provable security.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.30 no.4
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• pp.133-140
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• 2007

This study aims to design and implement a learning evaluation system using .NET which is developed by Microsoft. .NET technology supports higher processing speed than ASP technology. The learning evaluation system is based on the web, consists of administrator module, questioner module and student module. The functions of the system, i.e., providing test questions, performing test, and evaluating result of test are achieving on the web in real time. Even when many users use this system, the system is stable and has a speed response time.

• Journal of the Korean Society for information Management
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• v.11 no.1
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• pp.167-187
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• 1994

This project is to design and to implement an cornputenzed acquisition system by structured analysis technique for the Yomi university library. In result of desgmng, we added three subsystems, whlch are accession control, account, and print out system, to DOBIS/E acquisition system because we found that our DOBIS/E acquision system is able to use as we do ordenng and receiving in traditional process. DOBIS/E system and three added subsystems is closely related, and allow acquisition librarians to work more efficiently than before.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.