• Proceedings of the Korean Institute of Building Construction Conference
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• 2019.05a
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• pp.51-52
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• 2019

Currently in domestic, it is difficult to the evacuation in fire due to the building is higher. Therefore it is necessary to evacuation safety design of building. To conduct the evacuation fire design of building, it should be done the Evacuation Safety Verification. But it is not sufficient the Study about Evacuation Safety Verification in currently domestic. Therefore in this study, we conducted the evacuation safety verification using people who they can't the evacuation themselves. The method of verification, we suggest the comparative that people who they can't the evacuation themselves and available safety evacuation time. Available safety evacuation time is determined by determined method from disaster statistics of casualties or equivalence with current standard requirement. it is doing to objectively judge of evacuation safety design validity in building.

• Structural Engineering and Mechanics
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• v.71 no.6
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• pp.643-656
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• 2019

A new seismic design methodology was proposed for precast concrete diaphragms. This methodology adopts seismic design factors applied on top of current diaphragm design forces. These factors are aimed to produce diaphragm design strengths aligned with different seismic performance targets. These factors were established through extensive parametric studies. These studies used a simple evaluation structure with a single-bay rectangular diaphragm. The simple evaluation structure is suitable for establishment of the design factors over comprehensive structural geometry and design parameters. However, the application of the design factors to prototype structures with realistic layouts requires further verification and investigation. This paper presents diaphragm design of several precast concrete parking structures using the new design methodology and verification of the design factor through nonlinear dynamic time history analyses. The seismic behavior and performance of the diaphragm were investigated for the precast concrete parking structures. It was found that the design factor established for the new design methodology is applicable to the realistic precast concrete parking structures.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.7 s.250
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• pp.816-825
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• 2006

This paper describes the development of a web-based interference verification system in the mold design process. Although several commercial CAD systems furnish interference verification functions, those systems are very expensive and inadequate to perform collaborative works over the Internet. In this paper, an efficient and precision hybrid interference verification algorithm for the web-based interference verification system over the distributed environment has been studied. The proposed system uses lightweight CAD files produced from the optimally transformed CAD data through ACIS kernel and InterOp. Collaborators related to the development of a new product are able to verify the interference verification over the Internet without commercial CAD systems. The system reduces production cost, errors and lead-time to the market. Validity of the developed system is confirmed through case studies.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.755-758
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• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Speech Sciences
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• v.10 no.2
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• pp.35-43
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• 2003

General speaker verification systems improve their recognition performances by normalizing log likelihood ratio, using a speaker model and its background speaker model that are required to be verified. So these systems rely heavily on the availability of much speaker independent databases for background speaker model design. This constraint, however, may be a burden in practical and portable devices such as palm-top computers or wireless handsets which place a premium on computations and memory. In this paper, new approach for the GMM-based background model design used in portable speaker verification system is presented when the enrollment data is available. This approach is to modify three parameters of GMM speaker model such as mixture weights, means and covariances along with reduced mixture order. According to the experiment on a 20 speaker population from YOHO database, we found that this method had a promise of effective use in a portable speaker verification system.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.167-170
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• 2003

In this paper, a design and experiment of PCI Express Core verification Model is described. The model targeting Endpoint core verification is designed by using newly-emerging SystemC which is a system design language based on a new C++ class library and simulation engine. In the verification model, we developed a SystemC Host System model which act as a Root Complex and Device Driver dedicated to the PCI Express Endpoint RTL Core. The test of Host System Model is guided by scenarios which implements and acts point of Device Driver and Root Complex and shows the result of simulation. Also, We present the full structure of verification model and Host model.

• Proceedings of the IEEK Conference
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• summer
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• pp.285-288
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• 2004

In this paper, we present a design and experiment of PCI Express core verification model. The model targeting Endpoint core based on Verilog HDL is designed by newly-emerging SystemC, which is a new C++ class library based system design approach. In the verification model, we designed and implemented a SystemC host system model which acted as Root Complex and device driver dedicated to the PCI Express Endpoint RTL core. The verification process is scheduled by scenarios which are implemented in host model. We show that the model is useful especially for verifying the RTL model which has dependencies on system software.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4207-4213
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• 2012

Software quality is strongly associated with requirement quality. Accordingly, companies are trying effect for enhancing requirement quality. But, it is difficult to verify the requirement of specification format, which have to rely on abnormal business knowledge of analyst. Also, it is insufficient to normal methodology or automated technique for enhancing requirement quality of specification format. In this paper, we propose the process of requirement verification and automated verification tool for enhancing requirement quality. we compare the external view design and internal view design for verifying requirement. In the case study, we evaluate the feasibility of the proposed automated verification technique of requirement.