• Title/Summary/Keyword: Design Verification

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Design and Experimental Verification on a Towing Winch (예인윈치의 설계 및 실험적 검증)

  • Yang, Seung-Yun
    • Journal of Institute of Control, Robotics and Systems
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    • v.5 no.4
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    • pp.489-495
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    • 1999
  • This paper contains the design specification and detail design for a towing winch system. We analyze operating condition of the system and decide the design specification for the winch system, and also perform a detail design for the subsystem such as hydraulic winch system, control equipment and power supplier at the full scale development. The performance of designed towing winch is established by load tests and sea trial tests.

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A study on the VLSI design automation (VLSI 설계 자동화에 대한 연구)

  • 경종민
    • 제어로봇시스템학회:학술대회논문집
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    • 1986.10a
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    • pp.623-628
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    • 1986
  • This paper reviews various CAD(Computer-Aided design) or DA(Design Automation) procedures for specification, design and verification of VLSI chips. The growth and widening of engineering achievements and applicational varieties in this revisited field has been truly explosive for the last five years. Recent trends in VLSI/CAD area and their possible implications on the future evolution of DA society are briefly touched upon. The relative importance of chip specification and design capability within the whole Korean electronics infrastructure in the future is explained with several possible suggestions for coping with upcoming difficulties already being seen in this challenging yet promising area.

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Automatic Design of Hot Forging (열간단조의 자동설계)

  • 김대영;박종진
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 1997.03a
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    • pp.171-174
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    • 1997
  • In this study, a computer program was developed which generates automatically a drawing of the forging design in axisymmetric hot-forging of steel. The program designs a forging envelope from a machined part geometry according to forging design rules: parting line, draft angles, fillet and corner radii, minimum web and rib thicknesses. For the purpose of verification, the program was applied to a machined part from a factory. It was found that the generate forging design agreed well with the actual one used in the factory.

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Estimation Model-based Verification and Validation of Fossil Power Plant Performance Measurement Data (추정모델에 의한 화력발전 플랜트 계측데이터의 검증 및 유효화)

  • 김성근;윤문철;최영석
    • Journal of the Korean Society for Precision Engineering
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    • v.17 no.2
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    • pp.114-120
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    • 2000
  • Fossil power plant availability is significantly affected by gradual degradations of equipment as operation of the plant continues. It is quite important to determine whether or not to replace some equipment and when to replace the equipment. Performance calculation and analysis can provide the information. Robustness in the performance calculation can be increased by using verification & validation of measured input data. We suggest new algorithm in which estimation relation for validated measurement can be obtained using correlation between measurements. Input estimation model is obtained using design data and acceptance measurement data of domestic 16 fossil power plant. The model consists of finding mostly correlated state variable in plant state and mapping relation based on the model and current state of power plant.

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Design and Verification of PCI Controller in a Multimedia Processor (멀티미디어 프로세서의 PCI 컨트롤러 디자인 및 검증)

  • 이준희;남상준;김병운;임연호;권영수;경종민
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.499-502
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    • 1999
  • This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

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CDMA2000 lx Compliant Mobile Station Modem Design and Verification (CDMA2000 1x 이동국 모뎀의 설계 및 검정)

  • Gwon, Yun-Ju;Kim, Cheol-Jin;Im, Jun-Hyeok;Kim, Gyeong-Ho;Lee, Gyeong-Ha;Han, Tae-Hui;Kim, Yong-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.6
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    • pp.69-77
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    • 2002
  • In this paper, we present the CDMA2000 1x compliant mobile station modem chip (SCom5010) implemented in a 0.18${\mu}{\textrm}{m}$ CMOS technology.[1] ARM940T cached processor. TeakLite DSP core, and other peripheral blocks are integrated with the baseband modem chip. Also we show novel verification methodologies and explain how this chip can be used as an emulation processor.

Design and Implementation of Intrusion Detection System of Packet Reduction Method (패킷 리덕션 방식의 침입탐지 시스템 설계 및 구현)

  • JUNG, Shin-Il;KIM, Bong-Je;KIM, Chang-Soo
    • Journal of Fisheries and Marine Sciences Education
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    • v.17 no.2
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    • pp.270-280
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    • 2005
  • Many researchers have proposed the various methods to detect illegal intrusion in order to improve internet environment. Among these researches, IDS(Intrusion Detection System) is classified the most common model to protect network security. In this paper, we propose new log format instead of Apache log format for SSL integrity verification. We translate file-DB log format into R-DB log format. Using these methods we can manage Web server's integrity, and log data is transmitted verification system to be able to perform both primary function of IDS and Web server's integrity management at the same time. The proposed system in this paper is also able to use for wire and wireless environment based on PDA.

Efficient Simulation Acceleration by FPGA Compilation Avoidance (FPGA 컴파일 회피에 의한 효과적인 시뮬레이션 가속)

  • Shim, Kyu-Ho;Park, Chang-Ho;Yang, Sei-Yang
    • The KIPS Transactions:PartA
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    • v.14A no.3 s.107
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    • pp.141-146
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    • 2007
  • In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

Desing and Verification of Satellite B-ISDN Signalling Protocol (위성 B-ISDN 신호 프로토콜의 설계 및 검증)

  • Park, Seok-Cheon;Choe, Dong-Yeong;Gang, Seong-Yong
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.7
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    • pp.1909-1918
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    • 1999
  • The terrestrial/satellite hybrid network may replace or supply the terrestrial network in some areas or certain applications. For example, it may play a major role in global B-ISDN or in certain areas where the deployment of optical cable is not feasible, especially at the early stage of implementing terrestrial B-ISDN. Furthermore, it can play an important role in the development of B-ISDN due to their features of flexible wide coverage, independent of ground distances and geographical constraints, multiple access and multipoint broadcast. Also, satellite have the capability to supply terrestrial B-ISDN/ATM with flexible links for access networks as well as trunk networks. This paper describes the design and verification of the interworking protocol between terrestrial B-ISDN뭉 satellite network. For the verification, the designed interworking protocol is modeled by Petri-net and the model is analyzed by reachability tree.

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Development of Performance Estimate and Verification Process for Next Generation High-speed Prototype Train (차세대고속열차 차량시스 성능예측 및 성능검증 체계 개발)

  • Kim, Sang-Soo;Lee, Tae-Hyung;Choi, Sung-Hoon;Park, Choon-Soo;Han, In-Soo;Mok, Jin-Yong
    • Proceedings of the KSR Conference
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    • 2008.11b
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    • pp.555-560
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    • 2008
  • Korean Train Express (KTX) has been commercially operating and achieving elevation on transport capacity since 2004. And HSR-350x was developed and succeeded in testing of running over 350km/h. The new high-speed train development project, HEMU-400x project, has started since last year. To develop the train system, it is important how we progress the configuration of the system, design, manufacturing and test verification. The authors devised the performance estimate and verification process of the HEMU-400x and the project is performed following the developed processes.

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