• Journal of Ginseng Research
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• 제46권3호
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• pp.481-488
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• 2022

Background: Although the tumor-suppressive effects of ginsenosides in cell cycle have been well established, their pharmacological properties in mitosis have not been clarified yet. The chromosomal instability resulting from dysregulated mitotic processes is usually increased in cancer. In this study, we aimed to investigate the anticancer effects of ginsenoside Rg1 on mitotic progression in cancer. Materials and methods: Cancer cells were treated with ginsenoside Rg1 and their morphology and intensity of different protein were analyzed using immunofluorescence microscopy. The level of proteins in chromosomes was compared through chromosomal fractionation and Western blot analyses. The location and intensity of proteins in the chromosome were confirmed through immunostaining of mitotic chromosome after spreading. The colony formation assays were conducted using various cancer cell lines. Results: Ginsenoside Rg1 reduced cancer cell proliferation in some cancers through inducing mitotic arrest. Mechanistically, it inhibits the phosphorylation of histone H3 Thr3 (H3T3ph) mediated by Haspin kinase and concomitant recruitment of chromosomal passenger complex (CPC) to the centromere. Depletion of Aurora B at the centromere led to abnormal centromere integrity and spindle dynamics, thereby causing mitotic defects, such as increase in the width of the metaphase plate and spindle instability, resulting in delayed mitotic progression and cancer cell proliferation. Conclusion: Ginsenoside Rg1 reduces the level of Aurora B at the centromere via perturbing Haspin kinase activity and concurrent H3T3ph. Therefore, ginsenoside Rg1 suppresses cancer cell proliferation through impeding mitotic processes, such as chromosome alignment and spindle dynamics, upon depletion of Aurora B from the centromere.

• 한국전기전자재료학회논문지
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• 제37권3호
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• pp.332-336
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• 2024

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (R_on,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in R_on,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• 천문학회지
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• 제50권3호
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• pp.71-78
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• 2017

We present the characteristics and the performance of the new CCD camera system, SNUCAM-II (Seoul National University CAMera system II) that was installed on the Lee Sang Gak Telescope (LSGT) at the Siding Spring Observatory in 2016. SNUCAM-II consists of a deep depletion chip covering a wide wavelength from $0.3{\mu}m$ to $1.1{\mu}m$ with high sensitivity (QE at > 80% over 0.4 to $0.9{\mu}m$). It is equipped with the SDSS ugriz filters and 13 medium band width (50 nm) filters, enabling us to study spectral energy distributions (SEDs) of diverse objects from extragalactic sources to solar system objects. On LSGT, SNUCAM-II offers $15.7{\times}15.7$ arcmin field-of-view (FOV) at a pixel scale of 0.92 arcsec and a limiting magnitude of g = 19.91 AB mag and z=18.20 AB mag at $5{\sigma}$ with 180 sec exposure time for point source detection.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1284-1287
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• 2005

Peripheral pentacene region gives a significant influence on C-V characteristics of metal-oxide-pentacene capacitor structure. When the gate voltage goes toward negative, the effect of peripheral pentacene region becomes larger. Remaining gate DC bias constant and changing small signal frequency, the capacitance of peripheral pentacene changes along with frequency so that the total capacitance value also changes. The influence of peripheral pentacene region should be removed to measure accurate C-V characteristics, because it is hard to take into account the effect of the region quantitatively. After removing the influence of peripheral pentacene region, acceptor concentration, flat band voltage and depletion width of pentacene thin film are extracted from an accurate C-V curve as $1.58{\times}10^{17}cm^{-3}$, -1.54 V and 39.4 nm, respectively.

• 전자공학회논문지T
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• 제36T권2호
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• pp.8-13
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• 1999

본 논문은 MOSFET에서 2차원적 전위분포가 채널방향을 따라 준-선형적으로 변한다는 GCA(Gradual Channel Approximation)를 진성영역에서 수직 공핍층 폭이 준-선형적으로 변한다는 가정으로 대치하여 단채널 MOSFET에서도 적용 가능한 문턱전압의 해석적 모형을 제안하였다. 제안된 문턱전압 표현식은 유효 채널길이, 드레인전압, 기판(substrate) 바이어스 전압, 기판 도핑농도, oxide 두께 등에 대한 의존성을 통합적으로 나타내었으며, 계산된 결과는 BSIM3v3의 결과와 유사한 경향을 보이고 있다.

• Nuclear Engineering and Technology
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• 제53권4호
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• pp.1284-1288
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• 2021

In this work, we propose and design a GaN-based diode with a p-doped GaN (p-GaN) multi-well structure for high efficiency betavoltaic (BV) cells. The short-circuit current density (J_SC) and opencircuit voltage (V_OC) of the devices were investigated with variations of parameters such as the doping concentration, height, width of the p-GaN well region, well-to-well gap, and number of well regions. The J_SC of the device was significantly improved by a wider depletion area, which was obtained by applying the multi-well structure. The optimized device achieved a higher output power density by 8.6% than that of the conventional diode due to the enhancement of J_SC. The proposed device structure showed a high potential for a high efficiency BV cell candidate.

• 센서학회지
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• 제18권2호
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• pp.110-115
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• 2009

Polystyrene (PS) microspheres were used to good advantage as a template material to prepare macroporous $TiO_2$ thin films. This is enabled to run the thermal decomposition of the PS without the collapsing of the 3-D macroporous framework during the calcination step. $TiO_2$ thin films were deposited onto the colloidal templated substrates at room temperature by RF sputtering, and then samples were thermally treated at $450^{\circ}C$ for 40.min in air to remove the organic colloidal template and induce crystallization of the $TiO_2$ film. The macroporous $TiO_2$ thin film exhibited a quasi-ordered partially hexagonal close-packed structure. Burst holes, estimated to be formed during PS thermal decomposition, are seen as the hemisphere walls. the inner as well as the outer surfaces of the hollow hemispheres formed by the method of thermal decomposition can be easily accessed by the diffusing gas species. As a consequence, the active surface area interacting with the gas species is expected to be enlarged about by a factor of fourth as large as compared to that of a planar films. Also the thickness at neighboring hemisphere could be controlled a few nm thickness. If the acceptor density becomes as large that depletion width reaches those thickness, the device is in the pinch off-situation and a strong resistance change should be observed.

• 대한전자공학회논문지SD
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• 제41권3호
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• pp.15-30
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• 2004

본 연구는 게이트 매몰형 단채널 GaAs MESFET의 암전류 특성과 광전류 특성을 해석적으로 모델링하였다. 모델링 결과, 광조사에 의한 중성영역내의 광 전도도의 증가 보다 공핍층 내의 광 기전력 발생에 따른 공핍층 폭의 감소효과로 인한 드레인 전류의 증가가 크게 일어남을 보이고 있다. 중성영역의 케리어 밀도 변화는 1차원 케리어 연속 방정식으로부터 도출하였으며, 광 기전력 도출은 게이트-공핍층 경계면의 광전류와 열전자 방출전류가 상쇄되는 조건으로 도출하였다. 드레인전압 인가에 따른 단채널 소자의 채널 방향의 전계효과를 고려한 2차원 Poisson 방정식의 해법을 제안하였다. 모델링 결과를 시뮬레이션한 결과, 적절한 암전류 및 광전류 특성에 대한 통합적 모델이 얻어짐을 확인하였다.

• 대한전자공학회논문지
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• 제16권4호
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• pp.36-46
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• 1979

본 연구에서는 N -채널 실리콘 게이트 제작기술에 의하여 일련의 크기를 가지는 커페시터와 트렌지스터들이 제작되었다. 그 결과 다양한 이온 주입 조걸, 즉 B 의 경우 에너지 30keV∼60keV와 도오스 3 × 10 ~ 5 × 10 개/㎠ 그리고 P 의 경우 에너지 1001keV∼ 175keV와 4 ×10 ~ 7×11개/㎠ 도오스 영역에서 이들에 대한 D.C. 인자들의 측정치들이 이론적인 계산치들과 비상, 분석되어 있다. 이 D.C. 인자들에는 threshold전압, 공핍층의 폭, 게이트 산화물 두께, 표면상태, 가동 하전입자 밀도, 전자의 이동도 그리고 마지막으로 누설전류가 있는데, 이중 실제 MOS의 제작에 있어서 특허 중요한 threshold전압에 있어서는, 커어브트레이서와 C - V plot을 통하여 측정된 값들이 실제 재산에서 이용된 SUPREM II 컴퓨우터 프로그램에 의한 결과와 훌륭히 접근하고 있다. 그 밖에 여기나온 D.C.인자들 중에서 도오핑 수준은 기판의 역 게이트 바이어스에서 threshold전압들로 부터 계산된 것이고, 역전도는 정의된 subthreshold 기울기로 부터 추산된 것임을 밝혀 둔다. 마지막으로 이와같은 D. C. 시험 결과들을 종합적으로 평가해 볼 때 만들어진 커페시터와 트렌지스터들이 N -채널 MOS I. C. 기억소자용으로 적합함을 보여주고 있다.