• 융합신호처리학회논문지
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• 제5권4호
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• pp.325-332
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• 2004

본 논문에서는 DSSS-QPSK 베이스밴드 모뎀의 수신부를 단순화한 구조를 제안한다. 일반적인 수신기 구조는 정합 필터, 역확산기, DQPSK 디코더, 그리고 DLL(Delay Locked Loop) 부분으로 나누어진다. 본 논문에서는 정합 필터와 역확산기 구조가 비슷하다는 것을 이용하여 역확산기 부분에서 하는 역할을 정합 필터에서 담당하게 하였다. 이로 인하여 수신부에서의 연산량이 감소하였고 수신부 구조가 단순화되었다. 이러한 결과는 고속모뎀의 설계에 대단히 중요한 역할을 한다. 그리고 제안한 구조를 이용한 시뮬레이션과 실험을 통해 제안한 방법으로 수신부를 설계할 경우 연산속도가 증가하고 전반적인 구조 단순화를 얻을 수 있음을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• 전기전자학회논문지
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• 제15권1호
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• pp.23-28
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• 2011

본 논문에서는 CMOS 회로를 이용한 스프레드 스펙트럼 클록 발생기(SSCG)를 제안하고 구현하였다. 지연고정루프(DLL)의 저역통과필터(LPF)에 스프레드 스펙트럼 클럭 변조 로직에 의해 조절되는 전하펌프를 연결하여 전압 제어지연로직(VCDL)에 가해지는 제어전압을 조절함으로써 주파수의 변화를 유도하는 방법을 사용하였다. 이와 같은 구조에서는 변조 비율을 조절하기 위한 부가적인 회로가 필요없기 때문에 레이아웃 면적이 작아지게 되고 전력소모가 작아지는 장점을 갖는다. 스프레드 스펙트럼 클록 발생기는 UMC 0.25um 공정을 이용하여 시뮬레이션 및 레이아웃을 수행하였으며 전체 면적은 290um${\times}$120um^2 이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2004년도 하계학술대회
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• pp.41-45
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• 2004

본 논문에서는 DLL(Delay Locked Loop)를 응용하여 광통신 시스템에 응용할 수 있는 완전공핍 광 싸이리스터(Depleted Optical Thyristor)의 구동 Driver를 설계하였다. 광스위칭 소자로 활용될 DOT를 구동시키기 위해서는 Thyristor의 구조 특성을 고려할 때 강한 역방향 전압 펄스와 함께 높은 순방향 전류 펄스의 특성을 가지는 파형이 필요하다. 구동 Driver의 제작 공정은 삼성 CMOS $0.35{\mu}m$, 1 poly, 4 metal 공정을 사용하였고 시뮬레이션 결과 500 MHz 대역에서 DOT를 구동하기 위한 전압, 전류 특성을 가지는 파형을 얻을 수 있었다.

• 한국통신학회논문지
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• 제24권6A호
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• pp.871-880
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• 1999

본 논문은 광대역 CDMA 방식의 IMT-2000 단말기용 이동국의 PN 코드 위상 동기를 위한 추적기와 데이터를 복원하는 복조기회로 설계 및 구현에 대해서 기술한다. 먼저 동기 추적을 위한 회로는 넌코히어런트 방식을 사용하여 설계하였으며 동기 추적 과정에서 발생되는 클럭이 1/8 PN 칩의 해상도를 갖도록 설계하였다. 복조기 부분은 코히어런트 방식을 사용하여 설계하였으며 타임 트래킹 동작에 의해서 발생되는 클럭으로 생성된 PN 코드와 수신신호를 역확산하여 원래의 데이터를 복원하도록 설계하였다. 32.786 MHz의 구동 클럭과 4.096 MHz의 칩율을 사용하였으며 FPGA로 구현하였다. 또한 설계된 복조기는 32Kbps 음성 및 신호 채널에서 정상 동작함을 확인하였다. 성능 검증을 위하여 AWGN(Additive White Gaussian Noise) 7dB로 시뮬레이션하여 데이터 복원이 이루어 졌으며 무선 가입자망(WLL:wireless local loop)과 IMP-2000 변복조기 설계에 적용할 수 있음을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• The Journal of the Acoustical Society of Korea
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• 제24권3E호
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• pp.109-114
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• 2005

In this paper, we present a phase coherent all-digital transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater environments. It is designed in the digital domain except for transducers and amplifiers and implemented by using a multiple digital signal processors (DSPs) system. For phase coherent reception, conventional systems employed phase-locked loop (PLL) and delay-locked loop (DLL) for synchronization, but this paper suggests a frame synchronization scheme based on the quadrature receiver structure without using phase information. We show experimental results in the underwater anechoic basin at MOERI. The results show that the adaptive equalizer compensates frame synchronization error and the correction capability is dependent on the length of equalizer.