• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.15-24
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result. it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.8
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• pp.718-725
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• 2004

The real-time industrial network, often referred to as fieldbus, is an important element for intelligent manufacturing systems. Thus, in order to satisfy the real-time requirements of field devices, numerous fieldbus protocols have been announced. But, the application of fieldbus has been limited due to the high cost of hardware and the difficulty in interfacing with multi-vendor products. Therefore, as an alternative to fieldbus, the computer network technology, especially Ethernet (IEEE 802.3), is being adapted to the industrial environment. However, the crucial technical obstacle for Ethernet is its non-deterministic behavior that makes it inadequate for industrial applications where real-time data have to be delivered within a certain time limit. Recently, the development of switched Ethernet shows a very promising prospect for industrial application due to the elimination of uncertainties in the network operation resulting in much improved performance. This paper focuses on the application of the switched Ethernet with cascade structure for industrial communications. More specifically, this paper presents an analytical performance evaluation of switched Ethernet with cascade structure, and a case study about networked control system.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.172-179
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• 2015

Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.2
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• pp.148-153
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• 2012

In this paper, we propose a fault-tolerant QoS routing scheme based on interference awareness for providing both high throughput and minimum end-to-end delay for wireless sensor networks. With the proposed algorithm, it is feasible to find out the optimal transmission path between sensor nodes to the sink node by using cumulative path metric where real-time delivery, high energy efficiency and less interference are considered as in path selection. Finally, simulation results show that network throughput and delay can be improved by using the proposed routing scheme.

• Journal of Construction Engineering and Project Management
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• v.4 no.4
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• pp.41-46
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• 2014

Indian Construction industry is large, volatile, and requires tremendous capital outlays. Typically, the work offers low rates of return in relation to the amount of risk involved. A unique element of risk in the industry is the manner in which disputes and claims are woven through the fibre of the construction process. Delay is generally acknowledged as the most common, costly, complex and risky problem encountered in construction projects. Because of the overriding importance of time for both the Owner and the Contractor, it is the source of frequent disputes and claims leading to lawsuits. The growing rate of delays is adversely affecting the timely delivery of construction projects. Presently construction industries are facing a lot of problems, considering that a paper assess construction stakeholder's perception to the causes of delays and its effects on project delivery. And also one case study is considered in this paper to elicit responses from construction stakeholders. The primary aim of this paper is to identify the perceptions of the different parties regarding causes of delays, the allocation of responsibilities and the types of delays, and method of minimizing the construction delays.

• Journal of Power Electronics
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• v.17 no.3
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• pp.704-715
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• 2017

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1846-1855
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• 2015

In this paper, a precise relative positioning with TD(time differenced) carrier phase measurements from a low-cost GNSS(Global Navigation Satellite System) receiver is proposed and analysed. The proposed method is using carrier phase measurement from a single GNSS receiver that reference receiver is not required and stand alone positioning is possible. TD operation removes the troublesome integer ambiguity resolution problem, and if the time interval is short, other error, such as, ionospheric, tropospheric delay and ephemeris error are effectively eliminated. The error analysis of the proposed method shows that a precise and positioning with carrier phase is possible. The implemented system is evaluated using a real car experiments. The results show that the horizontal positioning error was less than 3m during 10 minutes experiments, which is 4 times more precise than the results of normal code based absolute positioning.

• Journal of Korean Society of Transportation
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• v.26 no.2
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• pp.47-56
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• 2008

Two-Lane Highway of Korea is important, Because it has the largeest portion of all roads of Korea. But it has only one lane for one direction. So, If Delays are happened by low-speed vehicles, high-speed vehicles should over-take through the other side of the road. This over-takings can generate the high possibility of traffic accidents and the severity of traffic accidents by over-takings is very high. Because it generates a head-on collision. But the level of Service that indicates the operation states of Two-Lane Highway is defined as a conception that explains the operation conditions of traffic safety etc. Whencalculating the Level of service. It is considered by only delays. So, in this paper, first, this author wants to present the calculation of delay-time by Total-Delay Rate. Second, by multiplying this delay-time by the costs of delays wants to present the method of calulates the total delay costs. Third, to consider the traffic accidents, After predicting the number of traffic accidents, As multipling this by the average of costs of traffic accidents. want to present the method to calculate Total traffic accidents costs. Forth, present the operation costs.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.4
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• pp.10-18
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• 2002

Network topology design is a multiobjective problem with various design components. The components such as cost, message delay and reliability are important to gain the best performance. Recently, Genetic Algorithms(GAs) have been widely used as an optimization method for real-world problems such as combinatorial optimization, network topology design, and so on. This paper proposed a method of Multi-objective GA for Design of the network topology which is to minimize connection cost and message delay time. A common difficulty in multiobjective optimization is the existence of an objective conflict. We used the prufer number and cluster string for encoding, parato elimination method and niche-formation method for the fitness sharing method, and reformation elitism for the prevention of pre-convergence. From the simulation, the proposed method shows that the better candidates of network architecture can be found.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.