• 제목/요약/키워드: Defense S/W Process

검색결과 14건 처리시간 0.022초

전기선폭발법으로 제조한 나노 W(텅스텐) 분말의 환원처리 및 방전플라즈마소결에 의한 조밀화 (Reduction and Spark Plasma Sintering of the W(Tungsten) Nanopowder Produced by the Electric Explosion of Wire Process)

  • 김지순;김철희;박은주;권영순;김진천;이성호;정동익
    • 한국분말재료학회지
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    • 제13권4호
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    • pp.269-277
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    • 2006
  • [ ${\beta}-W(W_3O)$ ] oxide layer on the surface of each W(tungsten) nanopowder produced by the electric explosion of wire(EEW) process were formed during the 1vol.% air passivation process. The oxide layer hindered sintering densification of compacts during SPS process. The oxide phase was reduced to the pure W phase during SPS. The W nanopowder's compacts treated by the hydrogen reduction showed high sintered density of 94.5%. after SPS process at $1900^{\circ}C$.

소프트웨어 제품계열 아키텍처 설계 프로세스 (A Study on Software Product-Line Architecture Design Process)

  • 오영배
    • 한국IT서비스학회지
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    • 제4권2호
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    • pp.47-59
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    • 2005
  • S/W product line is a S/W product or a set of S/W system, which has common functions. We can develop a specific S/W product, which satisfiesrequirements of a particular market segment and a mission in a specific domain by reusing the core asset such as the developed S/W architecture through the S/W product line. S/W development methodology based on the S/W product line can develop a S/W more easily and fast by reusing the developed S/W core asset. An advanced country of S/W technology selects S/W product line as a core field of S/W production technology, and support technology development. In case of USA, CMU/SEI (Carnegie Mellon University / Software Engineering Institute) developed product-line framework 4.0 together with the industry and the Ministry of National Defense. Europe is supporting the development of product line technology through ITEA(IT for European Advancement) program. In this paper, we aim to construct reference architecture of S/W product line for production of the S/W product line.

정보시스템 운영개념 연구: D정보자원관리시스템 사례 (An Operational Concept for Information Systems: A Case of the D Information Resource Management Information System)

  • 이상호;심승배
    • 한국IT서비스학회지
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    • 제5권1호
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    • pp.129-147
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    • 2006
  • This study analyzed an operational concept for the D Information Resource Management Information System (DIRMIS) to manage any IT resources effectively in defense area. We first deduced the concept of the information resource management (IRM) for defense area from the literature review, and we suggested a guideline, which has used in defense area, of the documentation for the operational concept description (OCD). Moreover, we developed the operational concept for the DIRMIS following the guideline. Especially, this study is a practical approach for suggesting of a case, and the share of accumulated cases will contribute to advance in System Integration (SI) industry as well as academic research.

AHP 기법을 통한 군용차량 개발시 운용자 요구사항 우선순위 설정 연구 (A Study on the Priority of Users' Requirements for the Development of Military Vehicles by Analytic Hierarchy Process)

  • 이범구;신용철;유황빈;조용건
    • 대한산업공학회지
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    • 제36권2호
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    • pp.117-124
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    • 2010
  • The military vehicles are an inevitable resource that is indispensible to successfully perform modern wars. Military vehicles used in the Korean Army are the copycats of American out-dated military vehicles, but limited to fulfill the specific requirements by the operators. Korean army are nowadays trying to launch a new developmental plan for military vehicles of new concepts by the Korean Army. This article, hence, extracts the necessary factors upon the advancement of military vehicles by the expertises with the operation of military vehicles as well as sufficient experiences about maintenance. Suggesting and setting up the priority, the result makes practical application for the decision of the development of military vehicles.

악성코드 대응 MPSM기반 실시간통합분석체계의 설계 및 구현 (Design and Implementation of a Real-time Integrated Analysis Framework based on Multiprocessor Search Modules against Malicious Codes)

  • 윤종문
    • 융합보안논문지
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    • 제15권1호
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    • pp.69-82
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    • 2015
  • 고도화되고 지능화가 예상되는 사이버 침해대응에 대해 효율적으로 대응키 위해서는 악성코드의 공격에 대해 기존 방어적 대응형태에서 공격적 전환개념이 요구되기에 이러한 환경을 근간으로 연구한 결과 기존의 OS, APPLICATION SYSTEM 등의 각 영역별 SINGLE-MODE 체계의 구조대비 Real-time에 의한 공통 전수 취약점 탐지 분석 개념으로 다단계기반의 탐지 및 분석개념(MPSM)을 연구하였다. 동시에 필요시 해당 정보자산과 직접적인 단독접속형태의 취약점 탐지 및 분석을 위해 API 기반의 전용하드웨어 플랫폼형태의 방안이 요구되어 짐과 동시에 이를 위해서는 H/W 및 S/W의 분리된 현재와 같은 2중화된 형태가 아닌 일체형의 H/W 타입의 플랫폼구조 기반 형태로 설계됨과 동시에 병행되어 빅데이타 분석에 의한 정보보안의 포렌직 측면을 고려할 시 항시 모니터링 되고 관리할 수 있는 구조로 연동 설계 등에 대해 제안하였다.

W-Band MMIC를 위한 T-형태 게이트 구조를 갖는 MHMET 소자 특성 (Characteristics of MHEMT Devices Having T-Shaped Gate Structure for W-Band MMIC)

  • 이종민;민병규;장성재;장우진;윤형섭;정현욱;김성일;강동민;김완식;정주용;김종필;서미희;김소수
    • 한국전기전자재료학회논문지
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    • 제33권2호
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    • pp.99-104
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    • 2020
  • In this study, we fabricated a metamorphic high-electron-mobility transistor (mHEMT) device with a T-type gate structure for the implementation of W-band monolithic microwave integrated circuits (MMICs) and investigated its characteristics. To fabricate the mHEMT device, a recess process for etching of its Schottky layer was applied before gate metal deposition, and an e-beam lithography using a triple photoresist film for the T-gate structure was employed. We measured DC and RF characteristics of the fabricated device to verify the characteristics that can be used in W-band MMIC design. The mHEMT device exhibited DC characteristics such as a drain current density of 747 mA/mm, maximum transconductance of 1.354 S/mm, and pinch-off voltage of -0.42 V. Concerning the frequency characteristics, the device showed a cutoff frequency of 215 GHz and maximum oscillation frequency of 260 GHz, which provide sufficient performance for W-band MMIC design and fabrication. In addition, active and passive modeling was performed and its accuracy was evaluated by comparing the measured results. The developed mHEMT and device models could be used for the fabrication of W-band MMICs.

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

  • Lee, Seung-Jun;Ha, Jong-Ok;Jung, Seung-Hwan;Yoo, Hyun-Jin;Chun, Young-Hoon;Kim, Wan-Sik;Lee, Noh-Bok;Eo, Yun-Seong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제11권4호
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    • pp.238-246
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    • 2011
  • A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique

  • Lee, Seongjoo;Lee, Jangwoo;Lee, Mun-Kyo;Nah, Sun-Phil;Song, Minkyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권5호
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    • pp.473-481
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    • 2013
  • A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

선박의 안전성 평가를 위한 네트워크 기반의 시뮬레이션 시스템 프레임워크 (Network-based Simulation System Framework for the Safety Assessment of Ship)

  • 이경호;김화섭;한선우;박종현;오준
    • 한국CDE학회논문집
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    • 제10권5호
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    • pp.356-364
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    • 2005
  • As a ritual of modern people is getting higher, the safety assessment of the structure related to people has become the most important part in the process of the design. Especially, in the case of a ship, as regulations about the safety of passengers and the pollution in the ocean are strictly reinforcing, the safety assessment has become the most important part in the process of the design. However, because the established safety assessment is mostly depend on the experienced theory, it is so difficult to assess the safety considering a lot of situations such as various ocean environments, the mistake of sailors and emergency situations. As the way to solve this problem, lately the study of the simulation using a computer has been processed. In this paper, we suggested network-based simulation system framework using HLA (High Level Architecture) among many kind of simulations to assess the safety of the ship. Because HLA has already become a standard of the future simulation system in the U.S. DoD(Department of Defense) and Korea army, we expect to raise the possibility in the future. In addition, because HLA makes a standard of documents and a reused component(Federate) of simulation(Federation) by OMT(Object Model Template) and RTI(Runtime Infrastructure), we expect that this study will be developing the safety assessment of ship as well as operation in warship and cooperation with another applications.

사이버 지휘통제 의사결정 지원을 위한 사이버 작전요소 분류 및 방책 평가 방안 연구 (A Study on Cyber Operational Elements Classification and COA Evaluation Method for Cyber Command & Control Decision Making Support)

  • 이동환;윤석준;김국진;오행록;한인성;신동규
    • 인터넷정보학회논문지
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    • 제22권6호
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    • pp.99-113
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    • 2021
  • 최근 육·해·공·우주에 이어 제 5전장 영역으로 사이버공간이 인식되면서 본격적으로 사이버공간을 작전 및 임무 영역으로 보는 활동에 관심이 집중되었다. 또한, 21세기는 4세대 전쟁방식으로 사이버공간을 기반으로 하는 사이버작전이 전개되고 있다. 이러한 환경에서 작전 수행은 지휘관의 의사결정에 따라 성공 여부가 판가름 된다. 따라서 이러한 의사결정의 합리성과 객관성을 높이기 위해서 체계적으로 방책(COA, Course Of Action)을 수립하고 선정하는 과정이 필요하다. 본 연구에서는 사이버작전 수행에 필요한 작전요소들을 분류하는 방안을 통하여 방책을 수립하고, 방책의 정량적 평가가 가능하다는 방향성을 제시하고자 한다. 이를 위해 작전 수행의 방책이 되는 사이버 작전요소 조합(COES, Cyber Operational Elements Set)을 구성하고 표적개발 과정에서 식별한 사이버 작전요소를 육하원칙(5W1H Method)을 기준으로 분류하는 방안을 제시한다. 또한 스턱스넷(STUXNET) 공격 사례에서 활용된 사이버 작전요소들을 제시한 분류 방안을 적용하여 사이버 작전요소 조합(COES)을 구성해 공격 방책들을 수립한다. 마지막으로 수립한 방책의 우선순위를 부여하고 최적의 방책 선정을 위해 방책의 정량적 평가를 수행하였다.