• Title/Summary/Keyword: Deep Trench

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Silicon-micromachined Microneedle for Suction and Injection of Bio Samples

  • Paik, Seung-Joon;Kim, Jong-Pal;Kim, Se-Tae;Park, Sang-Jun;Chung, Seok;Chang, Jun-Keum;Chun, Kuk-Jin;Cho, Dong-Il
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.178.6-178
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    • 2001
  • Silicon-micromachined microneedle for a biofluid diagnosis system is developed. To fabricate microneedles, two sets of processes are used. One is making buried microchannels in silicon wafer using silicon isotropic etch with a SF6 plasma and then trench-refilling. The other is releasing the body of the microneedle by deep silicon etch. The microneedle has a 4 mm-length and about 12 $\mu\textrm{m}$ diameter buried microchannel, a 1.5 mm$\times$l.5 mm-area reservoir, and about 180 $\mu\textrm{m}$thickness body. Preliminary results indicate that microneedles are capable of flowing fluidic samples. The microneedle with a buried microchannel is expected to be integrated with in vitro diagnosis systems and microfluidic devices.

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An Etch-Stop Technique Using $Cr_2O_3$ Thin Film and Its Application to Silica PLC Platform Fabrication

  • Shin, Jang-Uk;Kim, Dong-June;Park, Sang-Ho;Han, Young-Tak;Sung, Hee-Kyung;Kim, Je-Ha;Park, Soo-Jin
    • ETRI Journal
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    • v.24 no.5
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    • pp.398-400
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    • 2002
  • Using $Cr_2O_3$ thin film, we developed a novel etch-stop technique for the protection of silicon surface morphology during deep ion coupled plasma etching of silica layers. With this technique we were able to etch a silica trench with a depth of over 20 ${\mu}m$ without any damage to the exposed silicon terrace surface. This technique should be well applicable to fabricating silica planar lightwave circuit platforms for opto-electronic hybrid integration.

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The Electrical Characteristics of Power FET using Super Junction for Advance Power Modules

  • Kang, Ey Goo
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.360-364
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    • 2013
  • The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

Study on the Design of DC-DC Converter for Super Junction MOSFET Battery Charger of Electric Vehicles (전기자동차 배터리 충전을 위한 DC - DC컨버터용 Super Junction MOSFET 설계에 관한 연구)

  • Kim, Bum June;Hong, Young Sung;Sim, Gwan Pil;Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.8
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    • pp.587-590
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    • 2013
  • Release competition and development of eco-friendly vehicles have been conducted violently also automaker, it will be a high growth industry of the charger and battery, which is the driving source of the motor of an electric vehicle. Reduces the on-resistance power elements DC - DC converter for battery charger for electric vehicles, must minimize switching losses. Should have a low on-resistance power than existing products. Compare the Super Junction MOSFET and Planar MOSFET, As a result, super junction MOSFET improve on about 87.4% on-state voltage drop performance than planar MOSFET.

Reverse-Conducting IGBT Using MEMS Technology on the Wafer Back Side

  • Won, Jongil;Koo, Jin Gun;Rhee, Taepok;Oh, Hyung-Seog;Lee, Jin Ho
    • ETRI Journal
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    • v.35 no.4
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    • pp.603-609
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    • 2013
  • In this paper, we present a 600-V reverse conducting insulated gate bipolar transistor (RC-IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC-IGBT uses the deep reactive-ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC-IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.

The 29 May 2004 Offshore Southeast Coast of Korea Earthquake Sequence: Shallow Earthquakes in the Ulleung Back-arc basin, East Sea (Sea of Japan)

  • Kim, Won-Young;Noh, Myung-Hyun;Choi, Ho-Sun
    • Journal of the Korean Geophysical Society
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    • v.9 no.3
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    • pp.249-262
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    • 2006
  • The 29 May 2004 offshore Uljin, Korea earthquake was predominantly thrust-faulting at a depth of approximately 12 (±2) km. The mainshock attained the seismic moment of M0 =5.41 (±1.87)  1016 N m (Mw = 5.1). The focal mechanism indicates a subhorizontal P-axis trending 264° and plunging 2°. The orientation of P- and T-axis is consistent with the direction of absolute plate motion generally observed within the plates, hence the cause of the May 29 shock is the broad-scale stress pattern from the forces acting on the downgoing slab along the Japan trench and inhibiting forces balancing it. The 29 May 2004 earthquake occurred along a deep seated (~12 km), pre-existing feature that is expressed on the surface as the basement escarpment along the western and southern slopes of the Ulleung basin. The concentrated seismicity along this basement escarpment suggests that this feature may qualify as a seismic zone - the Ulleung basement escarpment seismic zone (UBESZ).

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Diagenesis of the Carbonate Rocks of the Seamounts In the Federated States of Micronesia, Central Pacific (중앙태평양 마이크로네시아 군도 해저산 일원에서 발견되는 탄산염암의 속성작용)

  • Woo, Kyung-Sik;Choi, Yoon-Ji;Lee, Kyeong-Yong;Kang, Jung-Keuk;Park, Byong-Kwong
    • The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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    • v.3 no.4
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    • pp.214-227
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    • 1998
  • This study was carried out to investigate the composition and diagenesis of the carbonate rocks from the seamounts in the Federated States of Micronesia, Central Pacific. Most of the samples were dredged from the water depth of about 1000-3000 m mainly in Chuuk Island, Hunter Bank, Caroline Ridge and Yap Trench. The carbonate rocks are either pelagic sediment mainly of planktonic foraminifera or shallow-marine sediment of corals, calcareous algae, mollusks and echinoderms. The rocks are altered texturally and chemically, except for those from the Hunter Bank and Yap A. The presence of shallow-marine cements suggests that the carbonate sediment has been subsided or reworked to the present water depth after deposition in shallow-marine environments. The texture of the carbonate sediment is reminiscent of meteoric diagenesis; however, the stable carbon isotopic composition of the altered rock samples shows affinity with that of sea water and the oxygen isotopic values are slightly enriched or same as compared to those of unaltered samples. These stable isotopic data suggest that the carbonate sediment of the study area has been diagenetically altered in the present deep-marine environment.

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Predicting the influent properties in an infiltration trench through deep learning analysis (딥러닝 분석을 통한 침투도랑 내 유입수 성상 예측분석)

  • Jeon, Minsu;Choi, Hyeseon;Geronimo, Franz Kevin;Heidi, Guerra;Jett, Reyes Nash;Kim, Leehyung
    • Proceedings of the Korea Water Resources Association Conference
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    • 2022.05a
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    • pp.363-363
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    • 2022
  • LID 시설에 대한 모니터링은 인력을 활용한 실강우 모니터링을 진행하고 있으나 LID 시설은 소규모 분산형시설로서 인력을 동원한 식생고사, 강우시 모니터링, 현장답사 등 꾸준한 시설확인에 한계가 있으며, LID 시설을 조성한 이후 적정한 유지관리 방법(주기, 빈도, 항목 등)을 인지하지 못하여 막힘현상, 효율저하, 식물고사 등의 문제가 발생한다. 따라서 본연구에서는 딥러닝 분석을 활용하여 강우시 강우모니터링 자료와 LID 시설 내 센서를 통해 측정된 자료를 통해 침투도랑 내 유입수 성상에 대한 예측분석을 수행하였다. 심지 내 LID 시설에 유입되는 오염물질을 예측을 위한 딥러닝 분석을 위해 과거 실강우시 모니터링 자료(TSS, COD, TN, TP)와 대기센서(대기습도, 대기온도, 강수량, 미세먼지) 데이터를 활용하여 딥러닝 모델에 대한 적용가능성 평가를 수행하였다. 측정항목에 대한 상관성 분석을 수행하였으며, 딥러닝 모델은 Tenser Flow를 이용하여 DNN(Deep Neural Network)모델을 활용하여 분석하였다. DNN 모델에 대한 MSE값은 0.31로 분석되었으며, TSS에 대한 평균 50.6mg/L로 분석되었으며, COD 평균 98.7 mg/L로 나타났다. TN의 평균 2.21 mg/L로 분석되었으며, TP 평균 0.67 mg/L로 나타났다. 상관계수분석결과 TSS는 0.53로 분석되었으며, TN과 TP의 상관계수는 0.10, 0.56으로 나타났다. COD의 상관계수는 0.63으로 TSS와 COD, TP에 대한 예측이 된 것으로 분석되었다. 딥러닝을 통한 LID 시설 내 농도변화 예측시 강우시 센서데이터 값은 조밀해야하며 오염물질 농도와 상관성이 높은 항목들에 대해 계측과 실강우 모니터링 자료를 축적하여 미래에 대한 활용성을 높여야 한다.

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The Effects of the Annealing on the Reflow Property of Cu Thin Film (열처리에 따른 구리박막의 리플로우 특성)

  • Kim Dong-Won;Kim Sang-Ho
    • Journal of Surface Science and Engineering
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    • v.38 no.1
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    • pp.28-36
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    • 2005
  • In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16~0.24 11m with aspect ratio of 4.17~6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

레이저 결정화 다결정 실리콘 기판에서의 게이트 산화막두께에 따른 1T-DRAM의 전기적 특성

  • Jang, Hyeon-Jun;Kim, Min-Su;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.201-201
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    • 2010
  • DRAM (dynamic random access memory)은 하나의 트랜지스터와 하나의 캐패시터의 구조 (1T/1C)를 가지는 구조로써 빠른 동작 속도와 고집적에 용이하다. 하지만 고집적화를 위해서는 최소한의 캐패시터 용량 (30 fF/cell)을 충족시켜 주어야 한다. 이에 따라 캐패시터는 stack 혹은 deep trench 구조로 제작되어야 한다. 위와 같은 구조로 소자를 구현할 시 제작공정이 복잡해지고 캐패시터의 집적화에도 한계가 있다. 이러한 문제점을 보완하기 위해 1T-DRAM이 제안되었다. 1T-DRAM은 하나의 트랜지스터로 이루어져 있으며 SOI (silicon-on-insulator) 기판에서 나타나는 floating body effect를 이용하여 추가적인 캐패시터를 필요로 하지 않는다. 하지만 SOI 기판을 이용한 1T-DRAM은 비용측면에서 대량생산화를 시키기는데 어려움이 있으며, 3차원 적층구조로의 적용이 어렵다. 하지만 다결정 실리콘을 이용한 기판은 공정의 대면적화가 가능하고 비용적 측면에서 유리한 장점을 가지고 있으며, 적층구조로의 적용 또한 용이하다. 본 연구에서는 ELA (eximer laser annealing) 방법을 이용하여 비정질 실리콘을 결정화시킨 기판에서 1T-DRAM을 제작하였다. 하지만 다결정 실리콘은 단결정 실리콘에 비해 저항이 크기 때문에, 메모리 소자로서 동작하기 위해서는 높은 바이어스 조건이 필요하다. 게이트 산화막이 얇은 경우, 게이트 산화막의 열화로 인하여 소자의 오작동이 일어나게 되고 게이트 산화막이 두꺼울 경우에는 전력소모가 커지게 된다. 그러므로 메모리 소자로서 동작 할 수 있는 최적화된 게이트 산화막 두께가 필요하다. 제작된 소자는 KrF-248 nm 레이저로 결정화된 ELA 기판위에 게이트 산화막을 10 nm, 20 nm, 30 nm 로 나누어서 증착하여, 전기적 특성 및 메모리 특성을 평가하였다.

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