• Journal of Communications and Networks
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• 제5권1호
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• pp.82-89
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• 2003

In this paper, an efficient threshold-based filtering (TF) buffer management scheme is proposed. The TF is capable of minimizing the overall loss performance and improving the fairness of buffer usage in a shared buffer packet switch. The TF consists of two mechanisms. One mechanism is to classify the output ports as sctive or inactive by comparing their queue lengths with a dedicated buffer allocation factor. The other mechanism is to filter the arrival packets of inactive output ports when the total queue length exceeds a threshold value. A theoretical queuing model of TF is formulated and resolved for the overall packet loss probability. Computer simulations are used to compare the overall loss performance of TF, dynamic threshold (DT), static threshold (ST) and pushout (PO). We find that TF scheme is more robust against dynamic traffic variations than DT and ST. Also, although the over-all loss performance between TF and PO are close to each other, the implementation of TF is much simpler than the PO.

• 산업경영시스템학회지
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• 제44권3호
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• pp.22-32
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• 2021

To meet rapidly changing market demands, manufacturers strive to increase both of productivity and diversity at the same time. As a part of those effort, they are applying flexible manufacturing systems that produce multiple types and/or options of products at a single production line. This paper studies such flexible manufacturing system with multiple types of products, multiple Bernoulli reliability machines and dedicated buffers between them for each of product types. As one of the prevalent control policies, priority based policy is applied at each machines to select the product to be processed. To analyze such system and its performance measures exactly, Markov chain models are applied. Because it is too complex to define all relative transient and its probabilities for each state, an algorithm to update transient state probability are introduced. Based on the steady state probability, some performance measures such as production rate, WIP-based measures, blocking probability and starvation probability are derived. Some system properties are also addressed. There is a property of non-conservation of flow, which means the product ratio at the input flow is not conserved at the succeeding flows. In addition, it is also found that increased buffer capacity does not guarantee improved production rate in this system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권8호
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• pp.3542-3566
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• 2018

In this paper, we investigate a buffer-aided wireless powered cooperative communication network (WPCCN), in which the source and relay harvest the energy from a dedicated power beacon via wireless energy transfer, then the source transmits the data to the destination through the relay. Both the source and relay are equipped with an energy buffer to store the harvested energy in the energy transfer stage. In addition, the relay is equipped with a data buffer and can temporarily store the received information. Considering the buffer-aided WPCCN, we propose two buffer-aided relaying protocols, which named as the buffer-aided harvest-then-transmit (HtT) protocol and the buffer-aided joint mode selection and power allocation (JMSPA) protocol, respectively. For the buffer-aided HtT protocol, the time-averaged achievable rate is obtained in closed form. For the buffer-aided JMSPA protocol, the optimal adaptive mode selection scheme and power allocation scheme, which jointly maximize the time-averaged throughput of system, are obtained by employing the Lyapunov optimization theory. Furthermore, we drive the theoretical bounds on the time-averaged achievable rate and time-averaged delay, then present the throughput-delay tradeoff achieved by the joint JMSPA protocol. Simulation results validate the throughput performance gain of the proposed buffer-aided relaying protocols and verify the theoretical analysis.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.94-97
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• 1999

In this paper, a new real-time neural network connection admission controller is proposed. The proposed controller measures traffic flows, cell loss rate and cell delay periodically each classes. The Neural network learns the relation between those measured information and service quality by real-time. Also the proposed controller uses the DWRR multiplexer with buffer dedicated to every traffic source in order to measure the delay that cells experience in buffer. Experimental result shows that the proposed method can control effectively heterogeneous traffic sources with diverse QoS requirement.

• 한국음향학회지
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• 제8권5호
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• pp.95-101
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• 1989

일반 DSP들은 새로운 algorithm 및 응용 system의 개발을 위해서 전용 development system 및 simulator가 필수 불가결의 요소이다. 그러나 대부분 development system은 일반화된 내부 구조에 의해 그 유연성에 한계가 존재한다. 본 연구에서는 A/D입력과 D/A출력 data를 저장하는 buffer의 길이를 program에 의해 1 sample 단위부터 최대 2K sample 단위까지 가변할 수 있도록 하고, 이들 buffer도 2중 구조로 하여 연속 신호의 처리가 가능도록 한 DSP평가용 system을 개발하였다.

• 전자공학회논문지B
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• 제31B권11호
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• pp.11-19
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• 1994

중앙처리장치와 디스크장치 사이의 큰 속도 차이로 인해 발생하는 병목현상은 디스크 입출력을 수반하는 작업의 처리시간에 많은 영향을 미친다. 본 논문에서는 디스크배열 시스템의 읽기요청에 대한 응답시간을 개선하기 위하여 기록전용버퍼를 내장할 것을 제안하고 그것의 스케쥴링정책과 개선효과를 정량적으로 분석한다. 시뮬레이션으로 비교분석함으로써 세 가지 스케쥴링 정책 가운데 부분스트라입결합 정책이 읽기와 기록응답시간 면에서 가장 효율적이며, 특히 분산형배열 시스템에 기록전용버퍼를 내장할 경우 요청율이 높을수록 읽기요청에 대한 응답시간의 개선효과가 크다는 것을 보인다.

• 대한전자공학회논문지TC
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• 제48권4호
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• pp.1-5
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• 2011

본 논문은 MBOA UWB SoC의 MAC 시스템 설계에 관한 것이다. 구현된 MBOA MAC 알고리즘은 일반적으로 널리 사용되고 있는 중앙의 마스터가 네트워크를 관리하는 방식이 아니라, 모든 디바이스가 네트워크를 구성하고 관리할 수 있는 분산 방식을 사용하고 있다. 따라서 MAC이 분산 네트워크를 구성하고 관리를 하기 때문에 메쉬 네트워크 구성이 용이하다. 시스템은 데이터 처리 속도를 최대화하기 위해서 캐쉬가 내장된 ARM926EJ를 내장하였고, 재사용 및 시스템 설계가 용이한 AMBA 버스를 사용하였다. 또한, 칩의 소모 전력을 최소화하기 위해 시스템 클럭 제어 알고리즘을 구현하였다. 그리고, 시스템 메모리 버퍼와 MAC 하드웨어간의 데이터 이동을 위하여 MAC 전용 DMA를 설계하였으며, Host와 시스템 메모리 버퍼간의 고속의 데이터 이동을 위하여 USB 2.0 블록의 전용 DMA를 사용하였다.

• 경영과학
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• 제28권3호
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• pp.15-29
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• 2011

In this paper, we consider a system working at both primary service and secondary service. A server can switch between the primary service and the secondary service or it can be assigned to secondary service as a dedicated server. A service policy is characterized by the number of servers dedicated to the secondary service and a rule for switching the remaining servers between two services. The primary service system is modelled as a Markovian queueing system and the throughput is a function of the number of servers, buffer capacity, and service policy. And the secondary service system has a service level requirement strategically determined to perform the service assigned. There is a revenue obtained from throughput and costs due to servers and buffers. We study the problem of simultaneously determining the optimal total number of servers, buffers, and service policy to maximize profit of the system subject to both an expected customer waiting time constraint of the primary service and a service level constraint of the secondary service and develop an algorithm which can be successfully applied with the small number of computations.

• 한국통신학회논문지
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• 제21권1호
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• pp.119-130
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• 1996

This paper is the part I of the full study about improved structure of fully interconnected ATM switch to develop the small sized switch element and practical implemention of switch network. This part I paper describes about proposed switch structure, performance evaluations and some of considerations to practical implementation. The proposed structure is constructed of two step buffering scheme in a filtered multiplexer. First step buffering is carried out by small sized dedicated buffers located at each input port. And second step buffering is provided by a large sized common buffer at the output port. To control bursty traffic, we use speed up factor in multiplexing and priority polling according to the levels of buffer occupancy. Proposed structure was evaluated by computer simulation with two evaluation points. One is comparision of multiplexing discipline between hub polling and priority polling. The ogher is overall which should be considered to improve the practical implementation.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1998년도 학술발표대회 논문집 제17권 2호
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• pp.223-226
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• 1998

In the Input Buffer Switch using the intial stage FIFO memory structure, It has pointed the Throughput limitation to the percent of 58.6 due to HOL(Head of Line) blocking in the DBP(Dedicated Buffer with Pointer) method, During that time, To overcome these problems, The prior papers have proposed the complicated Arbitration algorithms and Non-FIFO memory structures. and These showed the improved Throughput. But, Now, To design high speed ATM Switch which need to the tens of Giga bit/s or the tens of Tera bit/s. It has more difficulty in proceeding the priority of majority and the complicated Cell Scheduling, because of the problem in operating the control speed of the ratio of N to scanning each port and scheduling the Cell. In this paper, To overcome these problems, We could show more the improved performance than the existing DBP Window policy to design high speed ATM Switch.