• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.35-39
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• 2011

Error correcting codes with easy variability in code rate and codeword length in addition to powerful error correcting capability are required for present and future mobile multimedia communication systems. And low complexity is also needed for the compact mobile terminals. In general, the irregular random LDPC(low-density parity-check) code is known to have the superior performance among various LDPC codes. But it has inefficiency since the various parity check matrices for various services should be stored for encoding and decoding. The structured LDPC codes which can easily provide various rates and lengths are studied recently. Therefore, the flexibility, memory size, and error performance of various structured LDPC codes are compared and analyzed in this paper. And the most appropriate structured LDPC code is also suggested.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.141-150
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• 2010

In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is improved 3dB by increasing the number of iterations, 2 to 8, and interleaver length of a turbo encoder, 100 to 5000. The results in this paper can be applied to OFDM-based high-speed power line communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.34-42
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• 2012

Low density parity check (LDPC) code is widely used, since it shows superior performance close to Shannon limit and its decoding complexity is lower than turbo code. Recently, it is used as a channel code to decode Wyner-Ziv frames in distributed video coding (DVC) system. In this paper, we propose an efficient method to design the parity check matrix H of LDPC codes. In order to apply LDPC code to DVC system, the LDPC code should have rate compatibility. Thus, we also propose a method to merge check nodes of LDPC code to attain the rate compatibility. LDPC code is designed using ACE algorithm and check nodes are merged for a given code rate to maximize the error correction capability. The performance of the designed LDPC code is analyzed extensively by computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.1-7
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• 2012

The conventional Zhu's differential space-time modulation(DSTM) based on quasi-orthogonal design adopted a complex precoder in order to allow an independent joint detection of two complex symbols without any channel informations at a receiver. In this paper, by simply replacing the complex precoder used in Zhu's DSTM with a real precoder, a new DSTM is presented for four transmit antennas. The real precoder enables the receiver to decode two real symbols pair separately, and thus the new DSTM has greatly reduced decoding complexity compared to the Zhu's DSTM. By computer simulation results, the proposed scheme is shown to exhibit almost identical or improved error performance compared to the existing DSTMs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9C
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• pp.537-545
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• 2011

This paper analyzed performance of three dimensional turbo code and turbo ${\Phi}$ codes proposed in the next generation DVB-RCS systems. In the view of turbo ${\Phi}$ codes, we proposed the optimal permutation and puncturing patterns for triple binary input data. We also proposed optimal post-encoder types and interleaving algorithm for three dimensional turbo codes. Based on optimal parameters, we simulated both turbo codes, and we confirmed that the performance of turbo ${\Phi}$ codes are better than that of three dimensional turbo codes. However, the complexity of turbo ${\Phi}$ is more complex than that of three dimensional turbo codes by 18%.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Speech Sciences
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• v.10 no.3
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• pp.241-250
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• 2003

In this paper, we implemented the vocoder of variable rate by applying the SOLA-B algorithm to the G.729A to the TMS320C5416 in real-time. This method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. But the method applied to the existed G.729A and SOLA-B algorithm is caused the loss of speech quality in G.729A which is not reflected about length variation of speech. Therefore the proposed method is encoded according as it is modified the structure of LSP quantization table about the length of speech is reduced by using the SOLA-B algorithm. The vocoder of variable rate by applying the G.729A and SOLA-B algorithm is represented the maximum complexity of 10.2MIPS about encoder and 2.8MIPS about decoder in 8kbps transmission rate. Also it is evaluated 17.3MIPS about encoder, 9.9MIPS about decoder in 6kbps and 18.5MIPS about encoder, 11.1MIPS about decoder in 4kbps according to the transmission rate. The used memory is about program ROM 9.7kwords, table ROM 4.69kwords, RAM 5.2kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, the result of MOS test for evaluation of speech quality of the vocoder of variable rate which is implemented in real-time, it is estimated about 3.68 in 4kbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.1000-1010
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• 2006

This paper proposes a new architecture for DCT-based motion estimation and compensation. Previous methods do riot take sufficient advantage of the sparseness of 2-D DCT coefficients to reduce execution time. We first derive a recursion equation to perform DCT domain motion estimation more efficiently; we then use it to develop a wavefront array processor (WAP) consisting of processing elements. In addition, we show that the recursion equation enables motion predicted images with different frequency bands, for example, from the images with low frequency components to the images with low and high frequency components. The wavefront way Processor can reconfigure to different motion estimation algorithms, such as logarithmic search and three step search, without architectural modifications. These properties can be effectively used to reduce the energy required for video encoding and decoding. The proposed WAP architecture achieves a significant reduction in computational complexity and processing time. It is also shown that the motion estimation algorithm in the transform domain using SAD (Sum of Absolute Differences) matching criterion maximizes PSNR and the compression ratio for the practical video coding applications when compared to tile motion estimation algorithm in the spatial domain using either SAD or SSD.