• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1419-1426
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• 1997

A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.8
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• pp.74-83
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• 1997

In this paper, we propose a new fractal image decoding algorithm with fast convergence speed by using the data dependence and the improved initial image estimation. Conventional method for fractal image decoding requires high-degrdd computational complexity in decoding process, because of iterated contractive transformations applied to whole range blocks. On proposed method, Range of reconstruction imagte is divided into referenced range and data dependence region. And computational complexity is reduced by application of iterated contractive transformations for the referenced range only. Data dependence region can be decoded by one transformations when the referenced range is converged. In addition, more exact initial image is estimated by using bound () function in case of all, and an initial image more nearer to a fixed point is estimated by using range block division estimation. Consequently, the convergence speed of reconstruction iamge is improved with 40% reduction of computational complexity.

• Journal of Communications and Networks
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• v.6 no.3
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• pp.209-215
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• 2004

In this paper, a butterfly Log-MAP decoding algorithm for turbo code is proposed. Different from the conventional turbo decoder, we derived a generalized formula to calculate the log-likelihood ratio (LLR) and drew a modified butterfly states diagram in 8-states systematic turbo coded system. By comparing the complexity of conventional implementations, the proposed algorithm can efficiently reduce both the computations and work units without bit error ratio (BER) performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3A
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• pp.188-195
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• 2002

The M-algorithm for decoding convolutional codes can significantly reduce the complexity of the Viterbi algorithm by tracking a fixed number of survivor paths in each level of the decoding trellis. It is an easily-implementable algorithm suited for real-time processing of high-speed data. The algorithm, however, generates a sequence of catastrophic errors when the correct path is not included in the set of survivor paths. In this paper, the performance of the M-algorithm obtained from using various decoding complexity levels, frame lengths, and code constraint lengths is presented. The performance gain is quantified when the algorithm is used in conjunction with codes of increased constraint length. In particular, it is demonstrated the gain from the increased code free distance overcompensates the loss from the correct path being excluded from the survivors, when the frame length is short to moderate. Using 64 survivor paths, the signal-to-noise ratio gain obtained by increasing the constraint length from K=7 to K=9, 11, 15 is respectively 0.6, 0.75, and 08dB, when the frame of length L=100 has the frame error rate of 0.01%.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.784-789
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• 2006

In this paper, we propose a bitwise information decomposition algorithm for an M-PSK signal based on the Max-Log-MAP algorithm. In order to obtain the algorithm, we use a coordinate transformation from M-PSK to M-PAM signal space. Using the proposed algorithm, we analyze the performance of a Turbo iterative decoding method. The proposed algorithm can be applicable not only for a communication with PSK and iterative decoding method but for adaptive modulation and coding system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.322-328
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• 2009

This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the In[tanh(x)] and tanh-1 [exp(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about $0.3\;{\sim}\;0.8\;dB$ of BER performance compared with the existing modified sum-product algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.725-732
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• 2002

Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.

• Journal of Broadcast Engineering
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• v.23 no.3
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• pp.431-436
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• 2018

In this paper, a simple but effective algorithm to reduce the computational complexity of thumbnail generation and to improve image quality without aliasing artifacts is proposed. For the high speed decoding, the proposed algorithm performs partial decoding per $4{\times}4$ boundary in TU(Transform Unit), and preforms TU boundary in PU(Prediction Unit). The proposed method defines the weights based on intra prediction directions and estimates the thumbnail pixel by using that weights. this method remains thumbnail extraction time and improves thumbnail image quality compared with conventional algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.