• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.620-626
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• 2014

In this paper, we propose a parallel collaborative sphere decoder with a scalable architecture promising quasi-maximum likelyhood performance with a relatively small amount of computational resources. This design offers a hardware-friendly algorithm using a modified node operation through fixing the variable complexity of the critical path caused by the sequential nature of the conventional sphere decoder (SD). It also reduces the computational complexity compared to the fixed-complexity sphere decoder (FSD) algorithm by tree pruning using collaboratively operated node operators. A Monte Carlo simulation shows that our proposed design can be implemented using only half the parallel operators compared to the approach using an ideal fully parallel scheme such as FSD, with only about a 7% increase of the normalized decoding time for MIMO dimensions of $16{\times}16$ with 16-QAM modulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.4
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• pp.180-187
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• 2014

In this paper, a extension of a fixed-complexity sphere decoder (FSD) to perform interference signal detection and cancelling is proposed for downlink multiuser multiple input-multiple output (MIMO) communication system. It is based on the application of channel matrix expansion on generalized sphere decoder (GSD), and modification of the channel matrix ordering scheme to a FSD algorithm for interference detection. A Monte Carlo simulation shows that the proposed algorithm improves the receiver performance by 3 dB as compared to maximum likelihood detection without interference cancelling at 10% packet error rate in configuration of 702 Mbit/s datarate for four users respectively on IEEE802.11ac.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.303-309
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• 2006

By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

• Journal of Broadcast Engineering
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• v.15 no.1
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• pp.112-121
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• 2010

Distributed video coding is a coding paradigm that allows complexity to be shared between encoder and decoder, in contrast with conventional video coding. We propose that complexity balancing method of encoder/decoder by phase motion estimation algorithm. The encoder performs partial motion estimation. The result of the partial motion estimation is transferred to the decoder, and the decoder performs motion estimation within the narrow range. When the encoder can afford some complexity, complexity balancing is possible. The method proposed is able to know relativity between complexity balancing and coding efficiency. The coding efficiency increase rate by the encoder complexity increases is higher than that by the decoder complexity increases. The proposed method can control the complexity and coding efficiency according to devices' resources and channel conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.890-893
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• 2008

In this paper, we present a low complexity modified multi-level sphere decoder (SD) for multiple-input multiple-output (MIMO) systems employing quadrature amplitude modulation (QAM) signals. The proposed decoder, exploiting the multi-level structure of the QAM signal scheme, first decomposes the high-level constellation into low-level 4-QAM constellations, so-called sub-constellations. Then, it deploys SD in the sub-constellations in parallel. In addition, in the searching stage, it uses the optimal low-complexity sort method. Computer simulation results show that the proposed decoder can provide near optimal maximum-likelihood (ML) performance while it significantly reduces the computational load.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1419-1426
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• 1997

A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.

• Journal of Multimedia Information System
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• v.4 no.4
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• pp.179-188
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• 2017

The Internet Video Coding (IVC) standard is due to be published by Moving Picture Experts Group (MPEG) for various Internet applications such as internet broadcast streaming. IVC aims at three things fundamentally: 1) forming IVC patents under a free of charge license, 2) reaching comparable compression performance to AVC/H.264 constrained Baseline Profile (cBP), and 3) maintaining computational complexity for feasible implementation of real-time encoding and decoding. MPEG experts have worked diligently on the intellectual property rights issues for IVC, and they reported that IVC already achieved the second goal (compression performance) and even showed comparable performance to even AVC/H.264 High Profile (HP). For the complexity issue, however, there has not been thorough analysis on IVC decoder. In this paper, we analyze the IVC decoder in view of the time complexity by evaluating running time. Through the experimental results, IVC is 3.6 times and 3.1 times more complex than AVC/H.264 cBP under constrained set (CS) 1 and CS2, respectively. Compared to AVC/H.264 HP, IVC is 2.8 times and 2.9 times slower in decoding time under CS1 and CS2, respectively. The most critical tool to be improved for lightweight IVC decoder is motion compensation process containing a resolution-adaptive interpolation filtering process.