• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.735-738
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• 2005

This paper presents an AMBA-based IP that can perform the deblocking filtering operations required in the H.264 video compression. The deblocking filter circuit was optimized for area and performance. The AHB wrapper was added to the circuit to interface with the AMBA-based platform. The AMBA-compliant operation of the proposed IP was verified on the platform board with Xilinx Virtex2 XC2V600 FPGA and ARM9 processor.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.46-49
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• 2000

An iterative deblocking algorithm for DCT-compressed images using two-dimensional FIR filters adapted for local directionality of each block, is proposed. First, we introduce a set of simple lowpass filters, which are adapted for edges of different angles. In conventional deblocking methods based on lowpass-filtering and convex projections, a single filter is applied to a whole image. In the proposed method, on the other hand, a suitable filter is chosen out of the directional filters designed previously in every subimage (typically $8{\times}8$ block). Experimental results indicate that adaptive filtering improves PSNR at each iteration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.3
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• pp.1684-1699
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• 2017

The deblocking filter (DF) reduces blocking artifacts in encoded video sequences, and thereby significantly improves the subjective and objective quality of videos. Statistics show that the DF accounts for 5-18% of the total decoding time in high-efficiency video coding. Therefore, speeding up the DF will improve codec performance, especially for the decoder. In view of the rapid development of multicore technology, we propose a parallel DF scheme based on a modified order of accessing the coding tree units (CTUs) by analyzing the data dependencies between adjacent CTUs. This enables the DF to run in parallel, providing accelerated performance and more flexibility in the degree of parallelism, as well as finer parallel granularity. We additionally solve the problems of variable privatization and thread synchronization in the parallelization of the DF. Finally, the DF module is parallelized based on the HM16.1 reference software using OpenMP technology. The acceleration performance is experimentally tested under various numbers of cores, and the results show that the proposed scheme is very effective at speeding up the DF.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.89-96
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• 1998

Conventional block-based video coders induce annoying blocking artifacts in very low bitarte coding. We propose a delocking filter which is appropriate for real time operation in a conventional video decoder. The proposed algorithm uses on dimensional filtering across block boundaries horizontally and vertiaclly with two separate filtering modes. The mode decision is quite simple but is fully based on the characteristics of human visual system and video sequences. In flat regions, a strong smoothing filter is appliced; and in the other regions, a moew sophisticated smoothing filter, which is based on the frequency information around block boundaries, is used to reduce blocking artifacts without introuducing undesired blur. Eeven though the proposed deblocking filter is quite simple, simulation results show that it improves both subjective and objective image quality for various image features.

• ETRI Journal
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• v.33 no.2
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• pp.194-200
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• 2011

This paper presents a deblocking method for video compression in which the blocking artifacts are effectively extracted and eliminated based on both spatial and frequency domain operations. Firstly, we use a probabilistic approach to analyze the performance of the conventional macroblock-level deblocking scheme. Then, based on the results of the analysis, an algorithm to reduce the computational complexity is introduced. Experimental results show that the proposed algorithm outperforms the conventional video coding methods in terms of computation complexity while coding efficiency is maintained.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.2
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• pp.284-289
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• 2008

H.264/AVC among moving picture compression standard is the standard format for high compression rate and reliable video transimission. It generates blocking effects in video due to compressing video using block-based DCT and includes de-blocking filter to reduce blocking effect. Therefore, the filter makes the video over-smoothing and the quality of it is reduced. In this paper, we propose a improved de-blocking filter to solve the demerit. The proposed de-blocking filter redetermine the block boundary strength and apply the comer filtering to eliminate artifacts in low frequency domain. To evaluate the performance, we apply the proposed deblocking filter and exiting method to various video and evaluated the quality of image subjectively and objectively by analyzing the result. The simulation result shows the proposed method preserves the edge of video, reduces blocking effects and improves PSNR than the existing method.

• The Journal of Korean Association of Computer Education
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• v.13 no.4
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• pp.77-86
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• 2010

In this paper, we propose a real time post-processing visual enhancement technique to reduce the blocking artifacts in block based DCT decoded image for mobile devices that have allocation of the restricted resource. In order to reduce the blocking artifacts effectively even while preserving the image edge to the utmost, the proposed algorithm uses the deblocking filtering or the directional filtering according to the edge detection of the each pixel. After it is discriminated that the pixel to apply the deblocking filtering belongs again to the monotonous area, the weighted average filter with the adaptive mask is applied for the pixel to remove the blocking artifacts. On the other hand, a new directional filter is utilized to get rid of staircase noise and preserve the original edge component. Experimental results show that the proposed algorithm produces better results than those of the conventional algorithms in both subjective and objective qualities.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1506-1509
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• 2013

본 논문에서는 고성능 HEVC(High Efficiency Video Coding) 복호기 설계를 위한 효율적인 in-loop filter의 하드웨어 구조 설계에 대해 기술한다. in-loop filter는 deblocking filter와 SAO로 구성되며, 블록 단위 영상 압축 및 양자화 등에서 발생하는 정보의 손실을 보상하는 기술이다. 하지만 HEVC는 $64{\times}64$ 블록 크기까지 화소 단위 연산을 수행하기 때문에 높은 연산시간 및 연산량이 요구된다. 따라서 본 논문에서 제안하는 in-loop filter의 deblocking filter 모듈과 SAO 모듈은 최소 연산 단위인 $8{\times}8$ 블록 연산기로 구성하여 하드웨어 면적을 최소화하였다. 또한 SAO에서는 $8{\times}8$ 블록의 연산 결과를 내부레지스터에 저장하는 구조로 $64{\times}64$ 블록 크기를 지원하도록 설계하여 연산시간 및 연산량을 최소화 하였다. 제안하는 하드웨어 구조는 Verilog HDL로 설계하였으며, TSMC 칩 공정 180nm 셀 라이브러리로 합성한 결과 동작 주파수는 270MHz이고, 전체 게이트 수는 48.9k이다.