• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.12
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• pp.155-160
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• 2003

Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.511-517
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• 2006

The key issues in high power, high energy applications such as electromagnetic launchers include safety, reliability, flexibility, efficiency, compactness, and cost. To explore some of the issues, a control scheme for a large current wave-forming was designed, built and experimentally verified using a 2.4MJ pulse power system (PPS). The PPS was made up of eight capacitors bank unit, each containing six capacitors connected in parallel. Therefore there were 48 capacitors in total, with ratings of 22kV and 50kJ each. Each unit is charged through a charging switch that is operated by air pressure. For discharging each unit has a triggered vacuum switch (TVS) with ratings of 200kA and 250kV. Hence, flexibility of a large current wave-forming can be obtained by controlling the charging voltage and the discharging times. The whole control system includes a personal computer(PC), RS232 and RS485 pseudo converter, electric/optical signal converters and eight 80C196KC micro-controller based capacitor-bank module(CBM) controllers. Hence, the PC based controller can set the capacitor charging voltages and the TVS trigger timings of each CBM controller for the current wave-forming. It also monitors and records the system status data. We illustrated that our control scheme was able to generate the large current pulse flexibly and safely by experiments. The our control scheme minimize the use of optical cables without reducing EMI noise immunity and reliability, this is resulting in cost reduction. Also, the reliability was increased by isolating ground doubly, it reduced drastically the interference of the large voltage pulse induced by the large current pulse. This paper contains the complete control scheme and details of each subsystem unit.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.190-193
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• 2001

In order to verify the efficiency or availability and stability of photovoltaic(PV) generation systems, huge system apparatuses are needed, in general, in which an actual size of solar panel, a type of converter system and some amount of load facilities should be installed in a particular location. It is also hardly possible to compare a Maximum Power Point Tracking (MPPT) control scheme with others under the same weather and load conditions in an actual PV generation system. The only and a possible way to bring above-mentioned problem to be solved is to realize a transient simulation scheme for PV generation systems using real weather conditions such as insolation and surface temperature of solar cell. The authors, in this paper, introduces a novel simulation method, which is based on a real-time digital simulator (RTDS), for PV generation systems under the real weather conditions. Firstly, VI characteristic equation of a solar cell is developed as an empirical formula and reconstructed in the RTDS system, then the real data of weather conditions are interfaced to the analogue inputs of the RTDS. The outcomes of the simulation demonstrate the effectiveness of the proposed simulation scheme in this paper. The results shows that the cost effective verifying for the efficiency or availability and stability of PV generation systems and the comparison research of various control schemes like MPPT under the same real weather conditions are possible.

• Journal of IKEEE
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• v.14 no.3
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• pp.190-198
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• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• Journal of Biosystems Engineering
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• v.11 no.2
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• pp.14-22
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• 1986

This study was carried out to find a method which can be used to measure the soil moisture content of the soil bin exactly and quickly. And gypsum block is used as an instrument in measuring soil moisture content in the field of green house farming, etc.. However the characteristics of gypsum block, or the guide line of making gypsum block is not well introduced in Korea. So the information about gypsum block such as the density of gypsum, type of electrode, dimension of electrode, distance between electrodes, density of surrounding soil were included in this study and their effects on the relationship between soil moisture content and electrical resistance were investigated. The results of this study are as follows; 1. The grid type electrode was quicker in accessing the equilibrium condition and showed more sensitive response to the change of soil moisture content than the plate type electrode. 2. The longer the distance between the electrodes, the larger the electrical resistance, and the distance of 3 to 5 mm was recommended. 3. The larger the width of the electrode, the smaller the electrical resistance. However, there was no significance between the levels designed in this study. Considering the size of the gypsum block itself, the adaptible range of width may be 4 to 8 mm. 4. The higher the density of gypsum, the smaller the electrical resistance. And the block of lower density was broken down in the soil of higy moisture content. The optimum ratio of gypsum to water was 7:5. 5. The measuring system used in this study allowed simultaneous, multi-data acquisition. So this system using A/D converter can be applied to the measurement of soil moisture content of soil bin.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.295-296
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• 1998

With xeroradiography appearance, DR (Digital Radiography) system have been studying for X-ray detection using photoreceptor. Also detection method for receptor charge change have been developing variably. We use photoreceptor material of a-Se(Amorphous Selenium) with high DQE, high SNR(Signal to Noise Ratio) and high transformation efficiency of X-ray signals into electrical signals. After a-Se receptor is uniformly charged by using Arc discharge, X-ray is exposed. Then a-Se receptor produce subtle charge variation and MOSFET detect charge variations. The detected signal pass A/D converter and signal processing by PC. As results, the initial voltage is 8V. It has wide dynamic range needed digital radiography system. In this study, we obtained data with changing kVp(tube potential voltage) and fixed 8mAs(tube current by exposure time) in X-ray system. However MOSFET detector for X-ray signal is not tested X-ray mAs variations. But if MOSFET detector is tested X-ray mAs variation and exactly calibrated multichannel is made and noise-reduction is done, suitable DR system readout method will be done.