• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.94-104
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• 2000

The accuracy and reliability of the target tracking is very critical issue in the design of automotive collision warning radar A significant problem in multi-target tracking (MTT) is the target-to-measurement data association If an incorrect measurement is associated with a target, the target could diverge the track and be prematurely terminated or cause other targets to also diverge the track. Most methods for target-to-measurement data association tend to coalesce neighboring targets Therefore, many algorithms have been developed to solve this data association problem. In this paper, a new multi-target data association method based on order statistics is described The new approaches. called the order statistics probabilistic data association (OSPDA) and the order statistics joint probabilistic data association (OSJPDA), are formulated using the association probabilities of the probabilistic data association (PDA) and the joint probabilistic data association (JPDA) filters, respectively Using the decision logic. an optimal or near optimal target-to-measurement data association is made A computer simulation of the proposed method in a heavy cluttered condition is given, including a comparison With the nearest-neighbor CNN). the PDA, and the JPDA filters, Simulation results show that the performances of the OSPDA filter and the OSJPDA filter are superior to those of the PDA filter and the JPDA filter in terms of tracking accuracy about 18% and 19%, respectively In addition, the proposed method is implemented using a developed digital signal processing (DSP) board which can be interfaced with the engine control unit (ECU) of car engine and with the d?xer through the controller area network (CAN)

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.1
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• pp.109-119
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• 2013

This paper presents the design of the Safety Programmable Logic Controller (SPLC) used in the Nuclear Power Plants, an analysis of a reliability for the SPLC using a markov model. The architecture of the SPLC is designed to have the multiple modular redundancy composed of the Dual Modular Redundancy(DMR) and the Triple Modular Redundancy(TMR). The operating system of the SPLC is designed to have the non-preemptive state based scheduler and the supervisory task managing the sequential scheduling, timing of tasks, diagnostic and security. The data communication of the SPLC is designed to have the deterministic state based protocol, and is designed to satisfy the effective transmission capacity of 20Mbps. Using Markov model, the reliability of SPLC is analyzed, and assessed. To have the reasonable reliability such as the mean time to failure (MTTF) more than 10,000 hours, the failure rate of each SPLC module should be less than $2{\times}10^{-5}$/hour. When the fault coverage factor (FCF) is increased by 0.1, the MTTF is improved by about 4 months, thus to enhance the MTTF effectively, it is needed that the diagnostic ability of each SPLC module should be strengthened. Also as the result of comparison the SPLC and the existing safety grade PLCs, the reliability and MTTF of SPLC is up to 1.6-times and up to 22,000 hours better than the existing PLCs.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.371-374
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• 2004

Induction motors are a critical component of many industrial processes and are frequently integrated in commercially available equipment. Safety, reliability, efficiency, and performance are some of the major concerns of induction motor applications. Preventive maintenance of induction motors has been a topic great interest to industry because of their wide range application of industry. Since the use of mechanical sensors, such as vibration probes, strain gauges, and accelerometers is often impractical, the motor current signature analysis (MACA) techniques have gained murk popularity as diagnostic tool. Fault tolerant control (FTC) strives to make the system stable and retain acceptable performance under the system faults. All present FTC method can be classified into two groups. The first group is based on fault detection and diagnostics (FDD). The second group is independent of FDD and includes methods such as integrity control, reliable stabilization and simultaneous stabilization. This paper presents the fundamental FDD-based FTC methods, which are capable of on-line detection and diagnose of the induction motors. Therefore, our group has developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. This paper presents its architecture. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current, voltage, temperatures, vibration and speed of the motor. The DSPs share information from each sensor or DSP through DPRAM with hardware implemented semaphore. And it communicates the motor status through field bus (CAN, RS485). From the designed system, we get primitive sensors data for the case of normal condition and two abnormal conditions of 3 phase induction motor control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using CAN protocol.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1257-1259
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• 1996

In this paper, we introduce an integrated communication and control system(ICCS) for control of a crane. The system is integrated with a compasite technique as a network interfacing, a user interfacing and a system control for continuous process like as a container crane. The field-bus(Profibus) network module is used to interconnect each input/output module with main control unit. The MMI system for user interfacing is integrated with an ODBC-based data management tool and IECl131-based control logic design tool(Soft-Logic Designer:SLD). The each programmed control task in the main Controller is executed using a petri-net based scheduler.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.6
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• pp.716-722
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• 2014

In order to design the speed controller of the DC motor system, firstly, parameters estimation of the system must be preceded. In this paper, we proposed the application of genetic algorithm(GA) optimization in estimating the parameters of DC motor. Estimated models are considered both first and second order models, and each estimated model is optimized by minimizing three different types of the evaluation function of GA. Also, GA is imported in comparison with estimation result of numerical analysis method because of its power in searching entire solution space with more probability of finding the global optimum. Data for parameter estimation is acquired from input and output signals of the actual experiment device and the butterworth filter also designs for removing noise in the signals. Finally comparison between real data of the actual device and estimated models is presented to indicate effectiveness and resolution of proposed identification method.

• Journal of KIISE:Software and Applications
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• v.31 no.3
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• pp.255-266
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• 2004

In the Web-based information systems, separating the business process logic from the data and presentation logic brings about a wide range of advantages. However, this separation is not easily achieved; even the data logic may be not separated from the presentation layer. So, it requires to define an model for business processes, and then to map the model into the user's dynamic interface using the logic separating strategy. This paper presents a stylesheet method to recognize the process by extending XSLT (Extensible Stylesheet Language Transformations), in order to achieve the logic separation. To do this, it provides an specification of the business process, and a scheme that extracts business model factors and their interactions using a Petri-net notation to show the business model into the process point of view. This is an attempt to separate users' interaction from the business process, that is, dynamic components of interaction Web document from the process structure of Web applications. Our architecture consist mainly of an XSLT controller that is extended by a process control component. The XSLT controller is responsible for receiving the user requests and searching the relevant templet rule related to different user requests one by one. Separation of concerns facilities the development of service-oriented Web sites by making if modular. As a result, the development of service-oriented Web sites would be very easy, and can be changed without affecting the other modules, by virtue of the modularization concept. So, it is easy to develop and maintain the Web applications in independent manner.

• Journal of Korea Multimedia Society
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• v.20 no.3
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• pp.511-519
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• 2017

This Paper introduces the design and communication method between PLC (Programmable Logic Controller) and Arduino based on MODBUS Protocol. MODBUS connection can be established in a new or existing system very easily, therefore we used this protocol in our proposed system. In the field of automatic devices, multi-function serial port such as RS232, RS422, RS485, and so on creates a great convenience to the developer. This proposed system used RS485 as a key mediator for data exchanging on a connected network. We also believe that it will reduce the development cost in various automated industry because this system can be reused or can be implemented any such PLC installed machines. RS485 is used as a communication interface between PLC (as a slave) and Arduino (as a master), through which a reliable network is created for safe and fast communication. Furthermore, RS485 allows multiple devices(up to 32) to communicate at half duplex on a single pair of wires and provides a long connectivity area (up to 1200 meters) as compare to other device, which makes it a user-friendly for various devices in the automated industry. Moreover, Arduino can play as a mediator by connecting third party device and setup a communication network with PLC.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.5
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• pp.437-443
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• 2015

This paper presents face recognition based on the fusion of visible image and thermal infrared (IR) texture estimated from the face image in the visible spectrum. The proposed face recognition scheme uses a multi- layer neural network to estimate thermal texture from visible imagery. In the training process, a set of visible and thermal IR image pairs are used to determine the parameters of the neural network to learn a complex mapping from a visible image to its thermal texture in the low-dimensional feature space. The trained neural network estimates the principal components of the thermal texture corresponding to the input visible image. Extensive experiments on face recognition were performed using two popular face recognition algorithms, Eigenfaces and Fisherfaces for NIST/Equinox database for benchmarking. The fusion of visible image and thermal IR texture demonstrated improved face recognition accuracies over conventional face recognition in terms of receiver operating characteristics (ROC) as well as first matching performances.