• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.719-729
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• 2000

Prefetching aims at reducing memory latency by fetching, in advance, data that are likely to be requested by the processor in a near future. The effectiveness of prefetching is determined by how accurate the prediction on the needed instructions and data is. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and its performance evaluation, paying little attention to theoretical aspects of prefetching. This paper focuses on the theoretical aspects of instruction prefetching. For this purpose, we propose a clairvoyant prefetch model that makes use of perfect history information. Based on this theoretical model, we analyzed upper limits on the prefetch prediction accuracies of the SPEC benchmarks. The results show that the prefetch prediction accuracy is very high when there is no cache. However, as the size of the instruction cache increases, the prefetch prediction accuracy drops drastically. For example, in the case of the spice benchmark, the prefetch prediction accuracy drops from 53% to 39% when the cache size increases from 2Kbyte to 16Kbyte (assuming 16byte block size). These results indicate that as the cache size increases, most localities are captured by the cache and that instruction prefetching based on the information extracted from the references that missed in the cache suffers from prediction inaccuracies

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.7
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• pp.625-635
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• 2008

Portable multimedia players have some different properties compared to general multimedia file server. Some of those properties are single user ownership, relatively low hardware performance, I/O burst by user special functions, and short software development cycles. Though suitable for processing multiple user requests at a time, the general multimedia file systems are not efficient for special user functions such as fast forwards/backwards. Soml' methods has been proposed to improve the performance and functionality, which the application programs give prediction hints to the file system. Unfortunately, they require the modification of all applications and recompilation. In this paper, we present a file system that efficiently supports user special functions in embedded multimedia systems using file block allocation, buffer-cache, and prefetch. A prefetch algorithm, SPRA (SPeed-based PRefetch Algorithm) predicts the next block using I/O patterns instead of hints from applications and it is resident in the file system, so doesn't affect application development process. From the experimental file system implementation and comparison with Linux readahead-based algorithms, the proposed system shows $4.29%{\sim}52.63%$ turnaround time and 1.01 to 3,09 times throughput in average.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.30-43
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• 2008

Memory reference instructions such as loads or stores are critical factors that limit the processing power of processor. The prefetching technique is an effective way to reduce the latency caused from memory access. However, excessively aggressive prefetch leads to cache pollution so as to cancel out the advantage of prefetch. In this study, four filtering schemes have been compared and evaluated which dynamically decide whether to begin prefetch after referring a filtering table to decrease cache pollution. First, A bi-states scheme has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete state scheme has been introduced to be used as a reference for the comparative study. A block address lookup scheme has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the bi-states scheme, the contents of each entry have the fields the same as the complete state scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. Experimental results from commonly used general benchmarks and multimedia programs show that average cache miss ratio have been decreased by 10.5% for the block address lookup scheme(BAL) compare to conventional dynamic filter scheme(2-bitSC).

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.101-111
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• 2000

Resource managing is very difficult because the multimedia data compressed by a VBR shows a bit rate change within high range, Therefore, the VOD server should use the prefetch method in order to improve system utilization, such as prefetching data in the overload period by a meta table that is the reference pattern of MPEG data which is analyzed off line. This prefetch method will not result in a failure to display at overload, however, this method can not keep a minimum loading time and low costs, because the prefetched section is being maximizes. In this paper, we suggest another method that the system utilization can be improved using the fixed prefetched section to keep loading time and costs under a constant range at overload. But this technique will result in a failure to display, due to fixed prefetched section. Rut, in this paper we suggest a drop module that drops only the B frame in the GOP, consistently distributes a lower drop in media quality for the user.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.123-136
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• 2006

The prefetching technique is an effective way to reduce the latency caused memory access. However, excessively aggressive prefetch not only leads to cache pollution so as to cancel out the benefits of prefetch but also increase bus traffic leading to overall performance degradation. In this thesis, a prefetch filtering scheme is proposed which dynamically decides whether to commence prefetching by referring a filtering table to reduce the cache pollution due to unnecessary prefetches In this thesis, First, prefetch hashing table 1bitSC filtering scheme(PHT1bSC) has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete block address table filtering scheme(CBAT) has been introduced to be used as a reference for the comparative study. A prefetch block address lookup table scheme(PBALT) has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the PHT1bSC scheme, the contents of each entry have the fields the same as CBAT scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. On commonly used prefetch schemes and general benchmarks and multimedia programs simulates change cache parameters. The PBALT scheme compared with no filtering has shown enhanced the greatest 22%, the cache miss ratio has been decreased by 7.9% by virtue of enhanced filtering accuracy compared with conventional PHT2bSC. The MADT of the proposed PBALT scheme has been decreased by 6.1% compared with conventional schemes to reduce the total execution time.

• Journal of IKEEE
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• v.14 no.2
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• pp.69-75
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• 2010

A 3D graphics pipeline is largely divided into geometry stage and rendering stage. In this paper, we propose a method that accelerates a geometry processing in multi-core GP-GPU, using dual-phase structure. It can be improved by parallel data processing using SIMD of GP-GPU, dual-phase structure and memory prefetch. The proposed architecture improves approximately 19% of performance when it use all the features.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.163-172
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• 2004

Multimedia applications tend to access their data as a streaming pattern with regular intervals. This characteristic can be utilized in prefetching the multimedia data into cache memory so as to reduce their execution speeds. The reference-prediction prefetch algorithm predicts the memory address that seems to be used in the next time based on the previous history of memory references stored in the prediction reference table. This paper proposes a strategy to manipulate the reference prediction table which contains all of the data reference instructions to scalar and streaming data. We have recognized that the scalar reference instructions do not contribute to the data prefetching algorithm. Therefore, when replacing an element in the reference prediction table, the proposed algorithm preferentially selects the scalar reference instruction before the stream reference instruction. It makes the stream reference instruction to stay for a long time compared to the FIFO replacement policy, and eventually improves the performance of data prefetching.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.658-672
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• 2004

Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.