• Journal of the Korean Society of Clothing and Textiles
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• 제26권7호
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• pp.982-992
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• 2002

The purpose of this study is to investigate the clothing memory which affects apparel purchase behavior. The construction of clothing memory, the relationship between clothing memory and apparel purchase behavior, and the difference of clothing memory among persons by demographic variables are examined 746 female apparel consumers answer the questionnaire and data are analyzed by factor analysis, canonical correlation, Pearson correlation, and t-test. The result of this study are as follows; 1. There are three dimensions in the clothing memory which memory apparel purchase behavior; general memory about clothing, memory of appropriate clothing for oneself and memory of apparel purchase. 2. nothing memory affects apparel purchase behavior. General memory about clothing plays the most important role in the apparel purchase behavior especially in the amount of apparel purchase. 3. Unmarried young women with high income, high education level, and decent job have large amount of clothing memory.

• Journal of the Korea Society of Computer and Information
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• 제25권6호
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• pp.99-107
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• 2020

In this paper, we analyze the characteristics of mobile cache, which is used to improve the data access speed when executing applications on mobile devices, and verify the importance of mobile cache through a cache data access experiment. The mobile device market has grown at a fast pace over the past decade; however, battery limitations and size, price considerations restrict the usage of fast hardware. Thus, their performance are supplemented by using a memory buffer structure such as the cache memory. The analysis mainly focuses on cache size, hierarchical structure of cache, cache replacement policy, and the effect these features has on mobile performance. For the experimental data, we applied a data set from a microprocessor system study, originally used to test the cache performance. In the experimental results, the average data access speed on a mobile device showed a performance improvement of up to 10 times with the presence of cache memory than without. Accordingly, the cache memory was helpful for the performance improvement of a mobile device when the specifications were identical.

• Proceedings of the KSR Conference
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• 한국철도학회 2000년도 춘계학술대회 논문집
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• pp.180-187
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• 2000

This paper presents the system of analyzing data in memory of TCMS. This system can show physical data in memory to text and graphic : format. To transfer data from TCMS to this system, a large number of system have used to memory IC card. the method of using memory IC card as a intermediation has many points at issue, that is a speed of transmitting data, life time of IC card and identity of train system each other. So this paper proposes that the method of wireless LAM be adopted by this system to improve the week point of previous method and other method to better the method of wireless LAN.

• Journal of Information Technology Applications and Management
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• 제13권2호
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• pp.115-126
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• IEMEK Journal of Embedded Systems and Applications
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• 제6권6호
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• pp.383-391
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• 2011

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

• Journal of the Korea Society of Computer and Information
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• 제22권3호
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• pp.1-8
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• 2017

In this paper, we propose a new hybrid wear leveling technique for NAND Flash memory, called Time-Aware Wear Leveling (TAWL). Our proposal prolongs the lifetime of NAND Flash memory by using dynamic wear leveling technique which considers the wear level of hot blocks as well as static wear leveling technique which considers the wear level of the whole blocks. TAWL also reduces the overhead of garbage collection by separating hot data and cold data using update frequency rate. We showed that TAWL enhanced the lifetime of NAND flash memory up to 220% compared with previous wear leveling techniques and our technique also reduced the number of copy operations of garbage collections by separating hot and cold data up to 45%.

• Journal of the Korea Society for Simulation
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• 제12권4호
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• pp.95-102
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• 2003

Stream servers are for supplying multimedia stream data to users through the internet such as movies and music without discontinuation. A typical stream server is designed roughly by considering the characteristics of stream services and by employing processors, memory, PCI bus, Ethernet, TOE and disks. This study focuses on deciding the priority for using resources such as PCI bus, buffer memory and TOE buffer, which have limited capacities in a typical stream server. When the priorities for using limited resources are not given properly, the stream servers may not even function as originally designed. The simulation study shows that the top priority for using PCI bus for normal streaming services should be given to the operation that sends data from buffer memory to TOE buffer. Giving priority for using PCI bus to other operation such as sending data from disks to memory results in a deadlock phenomenon.

• The Transactions of the Korean Institute of Electrical Engineers
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• 제41권7호
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• pp.784-792
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• 1992

In this paper we design and implement a method for application programs to allow handling of large data files in DOS environment. In this method we use extended memory and hard disk as a data buffer. And we use a part of the conventional DOS memory as a buffer cache which allows the application program to use extended memory and hard disks transparently. Using buffer cache also allows us some speed improvement for the application program.

• Proceedings of the Korea Society for Simulation Conference
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• 한국시뮬레이션학회 2003년도 추계학술대회 및 정기총회
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• pp.67-74
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• 2003

Stream servers are for supplying multimedia stream data to users through the internet such as movies and musics without discontinuation. A typical stream server is designed roughly by considering the characteristics of stream services and by employing processors, memory, PCI bus, Ethernet, TOE and disks. This study focuses on deciding the priority for using resources such as PCI bus, buffer memory and TOE buffer, which have limited capacities in a typical stream server. The simulation study shows that the top priority for using PCI bus for normal streaming services should be given to the operation that sends data from buffer memory to TOE buffer Giving priority for using PCI bus to other operation such as sending data from disks to memory results in deadlock Phenomenon.

• Proceedings of the Korea Information Processing Society Conference
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• 한국정보처리학회 2020년도 추계학술발표대회
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• pp.12-15
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• 2020

Data access characteristics can directly affect the efficiency of the system execution. This research is to design an accurate predictor by using historical memory access information, where highly accessible data can be migrated from low-speed storage (SSD/HHD) to high-speed memory (Memory/CPU Cache) in advance, thereby reducing data access latency and further improving overall performance. For this goal, we design a locally weighted linear regression prefetch scheme to cope with irregular access patterns in large graph processing applications for a DARM-PCM hybrid memory structure. By analyzing the testing result, the appropriate structural parameters can be selected, which greatly improves the cache prefetching performance, resulting in overall performance improvement.