• KIISE Transactions on Computing Practices
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• v.22 no.1
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• pp.44-49
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• 2016

Recently, data has been growing dramatically along with the growth of social media and digital devices. A distributed memory processing system has been used to efficiently process large amounts of data. However, if a load is concentrated in a certain node in distributed environments, a node performance significantly degrades. In this paper, we propose a load balancing scheme to distribute load in a distributed memory environment. The proposed scheme replicates hot data to multiple nodes for managing a node's load and migrates the data by considering the load of the nodes when nodes are added or removed. The client reduces the number of accesses to the central server by directly accessing the data node through the metadata information of the hot data. In order to show the superiority of the proposed scheme, we compare it with the existing load balancing scheme through performance evaluation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.239-243
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• 1990

This paper presents a algorithm to improve accuracy and reliability in state estimation of contaminated bad data. The conventional algorithms for detection of bad data confront the problems of excessive memory requirements and long computation time. In order to overcome measurement compensation approach is proposed to reduce computation time and partitioned measurement error model has the advantage of remarkable reduction in computation time and memory requirements in estimated error computation. The proposed algorithm has been tested for IEEE sample systems, which shows its applicability to on-line power systems.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.113-118
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• 1986

Nowdays switching software designs are based on the concept of maximizing efficiency. This idea is to put through the most call, in the fastest time, using the fewest possible resources. So the memory usages are embossed one of the most important part to be considered in the switching software. This paper discusses the general concepts of switching software at first, then describes the switching data base from the view point of the access time, memory efficiency, and call processing environment.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.2
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• pp.144-153
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• 1991

This paper presents an algorithm to improve accuracy and reliability in the state estimation of contaminated bad data. The conventional algorithms for detection of bad data have the problems of excessive memory requirements and long computation time. In order to overcome these problems, a measurement compensation approach is proposed to reduce computation time, and the partitioned measurement error model has the advantage of remarkable reduction in computation time and memory requirements in estimated error computation. The proposed algorithm has been tested for IEEE sample systems, which shows its applicability to on-line power systems.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1687-1696
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• 1996

Most of the main memory database systems use two-phase locking(2PL)for concurrency control. The 2PL method is preferred over other methods for concurrency control because of its simplicity and common usage. However, conventional concurrency control solution will function poorly when the data are memory resident. In this paper, we propose a new optimistic concurrency control protocol for a main memory database system. In our proposed protocol, transaction conflict information is used in validation phase to improve data conflict resolution decisions. Our experiments show that the proposed protocol performs better than 2PL in terms of throughput for main memory database system enshrinements.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.461-468
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• 2001

Though shared virtual memory (SVM) system promise low cost solutions for high performance computing they suffer from long memory latencies. These latencies are usually caused by repetitive invalidations on shared data. Since shared data are accessed through synchronization and the patterns by which threads synchronizes are repetitive, a prefetching scheme bases on such repetitiveness would reduce memory latencies. Based on this observation, we propose a prefetching technique which predicts future access behavior by analyzing access history per synchronization variable. Our technique was evaluated on an 8-node SVM system using the SPLASH-2 benchmark. The results show the our technique could achieve 34%~45% reduction in memory access latencies.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.9
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• pp.327-336
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• 2015

Mobile game servers usually execute frequent dynamic memory allocation for generating the buffers that deal with clients requests. It causes to deteriorate the performance of game servers since it increases system workload and memory fragmentation. In this paper, we propose fixed-sized memory pool management method. Memory pool for the proposed method has a sequential memory structure based on circular linked list data structure. It solves memory fragmentation problem and saves time for searching the memory blocks which are required for memory allocation and deallocation. We showed the efficiency of the proposed method by evaluating the performance of dynamic memory allocation, through the proposed method and the memory pool management method based on boost open source library.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.