• International journal of advanced smart convergence
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• 제12권4호
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• pp.164-170
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• 2023

With the recent advances in AI (artificial intelligence) and HPC (high-performance computing) technologies, deep learning is proliferated in various domains of the 4th industrial revolution. As the workload volume of deep learning increasingly grows, analyzing the memory reference characteristics becomes important. In this article, we analyze the memory reference traces of deep learning workloads in comparison with traditional workloads specially focusing on read and write operations. Based on our analysis, we observe some unique characteristics of deep learning memory references that are quite different from traditional workloads. First, when comparing instruction and data references, instruction reference accounts for a little portion in deep learning workloads. Second, when comparing read and write, write reference accounts for a majority of memory references, which is also different from traditional workloads. Third, although write references are dominant, it exhibits low reference skewness compared to traditional workloads. Specifically, the skew factor of write references is small compared to traditional workloads. We expect that the analysis performed in this article will be helpful in efficiently designing memory management systems for deep learning workloads.

• International Journal of Computer Science & Network Security
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• 제24권4호
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• pp.192-196
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• 2024

The memory coherence problem occurs while mapping shared virtual memory in a loosely coupled multiprocessors setup. Memory is considered coherent if a read operation provides same data written in the last write operation. The problem is addressed in the literature using different algorithms. The big question is on the correctness of such a distributed algorithm. Formal verification is the principal term for a group of techniques that routinely use an analysis that is established on mathematical transformations to conclude the rightness of hardware or software behavior in divergence to dynamic verification techniques. This paper uses UPPAAL model checker to model the dynamic distributed algorithm for shared virtual memory given by K.Li and P.Hudak. We analyse the mechanism to keep the coherence of memory in every read and write operation by using a dynamic distributed algorithm. Our results show that the dynamic distributed algorithm for shared virtual memory partially fulfils its functional requirements.

• 사물인터넷융복합논문지
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• 제8권5호
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• pp.77-83
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• 2022

낸드 플래시 메모리는 구조적으로 쓰기 전 지우기(Erase-Before-Write) 동작이 요구된다. 이것을 해결하기 위해서는 데이터 업데이트 동작이 빈번히 발생하는 페이지(Hot data page)를 구분하여 별도에 블록에 저장함으로 해결할 수 있으며 이러한 Hot data를 분류하는 기법을 핫 데이터 판단기법이라 한다. MHF(Multi Hash Function Framework)기법은 데이터 갱신요청의 빈도를 시스템 메모리에 기록하고 그 기록된 값이 일정 기준 이상일 때 해당 데이터 갱신요청을 Hot data로 판단한다. 하지만 데이터 갱신요청에 빈도만을 단순히 카운트하는 방법으로는 정확한 Hot data로 판단에 한계가 있다. 또한 데이터 갱신요청의 지속성을 판단 기준으로 하는 기법의 경우 갱신요청 사실을 시간 간격을 기준으로 순차적으로 기록한 뒤 Hot data로 판단하는 방법이다. 이러한 지속성을 기준으로 하는 방법의 경우 그 구현과 운용이 복잡한 단점이 있으며 갱신요청에 빈도를 고려하지 않는 경우 부정확하게 판단되는 문제가 있다. 본 논문은 데이터 갱신요청에 빈도와 지속성을 함께 고려한 경량화된 핫 데이터 판단기법을 제안한다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2006년도 춘계학술발표대회
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• pp.1471-1480
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• 2006

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.125-134
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• 2016

NAND flash memory has unique characteristics like as 'out-place-update' and limited lifetime compared with traditional storage systems. According to out-of-place update scheme, a number of invalid (or called dead) pages can be generated. In this case, garbage collection is needed to reclaim invalid pages. Because garbage collection results in not only erase operations but also copy operations of valid (or called live) pages to other blocks, many garbage collection techniques have proposed to reduce the overhead and to increase the lifetime of NAND Flash systems. This techniques sometimes select victim blocks including cold data for the wear leveling. However, most of them overlook the cost of selecting victim blocks including cold data. In this paper, we propose a garbage collection technique named CAPi (Cost Age with Proportion of invalid pages). Considering the additional overhead of what to select victim blocks including cold data, CAPi improves the response time in garbage collection and increase the lifetime in memory systems. Additionally, the proposed scheme also improves the efficiency of garbage collection by separating cold data from hot data in valid pages. In experimental evaluation, we showed that CAPi yields up to, at maximum, 73% improvement in lifetime compared with existing garbage collections.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제10권9호
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• pp.235-242
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• 2021

기존 데이터 스크램블링 기법은 랜덤한 코드를 생성한다. 이와 다르게 우리는 생성하는 코드의 밀도를 다르게 만드는 가변 밀도 스크램블링 기법을 제안한다. 먼저 코드 밀도를 다르게 만드는 조건과 방법에 대해 설명한다. 다음으로 가변 밀도 스크램블링 기법을 플래시 메모리에 적용하여 특정 셀 상태가 더 많이 발생하도록 한다. 특히 플래시 메모리의 에러율을 제한하기 위하여, 가변 밀도 스크램블링 기법은 코드의 밀도를 조절하여 모든 셀 상태 중 중간 상태를 가지는 셀 비율을 높일 수 있다. 윈도우즈와 리눅스 시스템의 데이터에 가변 밀도 스크램블링 기법을 적용하였으며, 실험 결과는 가변 밀도 스크램블링 기법이 중간과 가까운 상태를 가지는 셀의 비율을 증가시킴을 보여준다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• 한국항공우주학회지
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• 제38권4호
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• pp.389-394
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• 2010

본 연구에서는 과학기술위성 2호와 비교 했을 때 고속의 데이터를 처리하고 대용량의 메모리를 관리해야하는 요구사항을 만족하기 위한 과학기술위성 3호 대용량 메모리 유닛의 설계 내용에 대해서 나타내었다. 이러한 요구사항을 만족하기 위해서, 두 개의 탑재체에서 각각 최대 100Mbps로 수신되는 데이터와 32Gb의 대용량 메모리를 처리하고 관리하는 역할을 FPGA가 직접 담당 하도록 설계하였다. 사용된 FPGA는 동작 속도가 빠르고 게이트 수가 많은 SRAM 기반의 Xilinx FPGA로써 우주 환경에서의 SEU를 극복하기 위해서 TMR 기법과 스크러빙 기법을 적용하고자 한다.

• 한국군사과학기술학회지
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• 제14권4호
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• pp.607-614
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• 2011

This paper describes the development of pulse code modulation(PCM) data recorder with design, implementation and environmental test. PCM serial data that diverged from telemetry encoder output is used as the input and is reformed to parallel signal through FPGA processing. Controllers construct the packet by the sector and record it into non-volatile memory. Compact flash(CF) memory for data storage media, USB interface for data downloading, and a software for operating status diagnosis and file format conversion are used.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권4호
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• pp.176-181
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• 2001

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.