• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.129-132
• /
• 2004

The iris image recognition system realization using DSP processor(TMS320DM642) for the faster real-time processing is presented on this paper. The system is composed of CCD camera, DSP processing and network part to link the communication. The system leads the iris recognition processing time to be faster. The simulation results in 0.9sec below approximately.

• The Journal of the Acoustical Society of Korea
• /
• v.16 no.2
• /
• pp.80-88
• /
• 1997

In this paper, the implementation of audio/data processor using ETRI DSP to support analog mode in digital/analog dual mode mobile phone is presented. Audio/data processor performs the wideband data processing, audio signal processing, demodulation function, and data rate conversion when it is operated in analog mode. These functions are programmed in assembly language, and then loaded to ETRI DSP together with vocoder program for the digital mode operation. This is a very efficient implementation of the dual mode cellular phone ASIC since the vocoder for the digital mode and audio/data processor for the analog mode are programmed together in the same hardware.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2001.06a
• /
• pp.89-92
• /
• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.7
• /
• pp.1147-1156
• /
• 2001

In this paper, a new design architecture of radar signal processor in real time is proposed. It has been designed and implemented under the consideration to minimize the inter-processor communication overhead and to maintain the coherence in Doppler pulse domain and in range domain. Its structure can be easily reconfigured and reprogrammed in accordance with an addition of function algorithm or a modification of operational scenario. As we designed a task configuration for parallel processing from measures of computation time for function algorithms and transmission time for results by signal processing, data exchange between processors for performing of function algorithms could be fully removed. Morocco-2 board equipped ADSP-21060 processor of Analog Devices inc. and APEX-3.2 developed for SHARC DSP were used to construct the radar signal processor.

• The Journal of the Acoustical Society of Korea
• /
• v.20 no.8
• /
• pp.19-23
• /
• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.12C
• /
• pp.727-737
• /
• 2011

This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.62-71
• /
• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10a
• /
• pp.685-691
• /
• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.7
• /
• pp.32-39
• /
• 1999

Digital signal processor (DSP) is used to obtain the peak value and the time difference of ultrasonic signals, to make digital filter, and to derive mathematical transformation from analog circuit. In this study, C-scan system and control program have been developed to high speed data acquisition. This system consists of signal processing parts (DSP, oscilloscope, pulser/receiver, digitizer), scanner, and control program. The developed system has been applied to a practical ultrasonic testing in overlay weld, and demonstrated high speed with precision

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.11
• /
• pp.1171-1177
• /
• 2009

A missile warning radar is an essential sensor for active protection system to detect antitank missile in all weather environments. This paper introduces missile warning radar for main battle tank and presents the results of the design and implementation of the radar signal processor using high speed multi-DSP. The key algorithms include adaptive CF AR, weighted linear fitting algorithm, S/W tracking capability, and threat decision and present test result.