• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.232-234
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• 2017

In this research, the BLDC motor 2 axis controller was designed using a dual core processor. The controller used TMS320F28377D which is TI's latest dual-core DSP, and the BLDC motor was selected with the position of resolver having high reliavility and the speed sensor built-in type motor.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.181-184
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• 1999

본 논문에서는 MPEG-1 계층 II와 MPEG-2 계층 II LSF 오디오 복호기를 OAK DSP Core를 이용하여 실시간 응용이 가능하도록 구현하였다. Ungrouping시 이용되는 테이블을 효율적으로 사용하였으며 합성필터부의 RAM과 ROM의 크기 그리고 각 부분의 연산에 필요한 연산량을 최적화하기 위하여 알고리듬을 효율적으로 적용하였고 불필요한 연산 부분을 제거하거나 최적화 하였다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.31-40
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• 2019

This paper proposes an adaptive PCIe system for TI C66x DSPs. Conventionally, the PCIe system provided by the C66x is a system dependent on the structure in which the primary core writes an application to the DSP memory through the PCIe interface, then activate the secondary core. Due to the dependency between the cores, when developing a project using a PCIe interface, the remaining cores have to be programmed with a concern of the primary core used as the PCIe interface. Therefore, in order to de-couple the connections among the cores, an adaptive PCIe system is proposed, in the paper, in which the cores operate independently compared to the conventional system. Since the core used as the PCIe interface only runs PCIe related operations in the new system, the remaining cores can be fully utilized without concerning the connections with the core for PCIe interface. In order to verify the feasibility of the proposed adaptive PCIe system, the implementations of LTE-A down link, and IEEE 802.11ac are carried out using the evaluation board which includes a TMS320C6670 chip. Altogether, these results support that we demonstrated that the digital signal processing systems with the PCIe Interface can be developed more rapidly by applying the proposed system.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.487-501
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• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.131-135
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• 2000

본 논문에서는 고성능 고정 소수점 DSP (Digital Signal Processor) 코어인 Vincent6 코어 [1]를 이용하여 ITU-T C.728 음성 부호화기를 실시간으로 구현하였다 G.728 은 16 kb/s전송률의 ITU-T표준 음성 부호화기이며, 입력신호는 8 kHz로 샘플링되며 샘플 당 16 bit 로 양자화된 PCM 신호이다. G.728 은 LD-CELP(Low Delay Code Excited Linear Prediction)라고도 하며, 알고리 듬 delay는 0.625ms 이다. Vincent6 DSP core 는 VLIW (Very-Long Instruction Word) 특성을 가지므로 다중 명령 (multiple instruction)을 수행할 수 있다 이를 위해서 G.728 annex G를 이용하여 고정 소숫점 연산으로 코드를 작성한 후, 이를 vincent6 어셈블리 코드로 구현하였다. 최종적으로 구현된 코드는 ITU-T 의 test vector 에 대 해 bit exact 한 결과를 보이며 34 MCPS (Million Cycles Per Second)의 계산량을 가지며 사용 메모리크기는 데이터 메모리가 약 9KByte, 프로그램 메모리가 약 57 KByte 이다.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.471-474
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• 2000

In this paper, we present multisample DSP coding technique for StarCore, SC 140 DSP. The multisample programming is a pipelining technique that exploits operand reuse both coefficients and variables within kernel. A coefficient or operand is loaded once from memory and then the value may be used by multiple ALUs. It is possible to evaluate one intermediate product from each of four output sample calculations in parallel . Therefore, parallelization has been achieved by processing multiple samples in parallel rather than multiple intermediate products belonging to only one sample. The benefits of decreasing the number of memory moves per sample is to increase the algorithm perforomance. In this paper, the multisample technique has been implemented in FIR filter calculation using Motorola StarCore DSP development tool.

• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.