• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.49-57
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• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.1
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• pp.8-15
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• 2011

This paper presents an effective method for detecting vehicles in front of the camera-assisted car during nighttime driving. The proposed method detects vehicles based on detecting vehicle headlights and taillights using techniques of image segmentation and clustering. First, in order to effectively extract spotlight of interest, a pre-signal-processing process based on camera lens filter and labeling method is applied on road-scene images. Second, to spatial clustering vehicle of detecting lamps, a grouping process use light tracking method and locating vehicle lighting patterns. For simulation, we are implemented through Da-vinci 7437 DSP board with visible light mono-camera and tested it in urban and rural roads. Through the test, classification performances are above 89% of precision rate and 94% of recall rate evaluated on real-time environment.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.253-258
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• 2021

In this paper, we developed a hardware and software platform of the real-time data logging system to verify radar FEM (Front-end Module) and signal-processing algorithms. We developed a hardware platform based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and implemented firmware software to verify the various FEMs. Moreover, we designed PC based software platform to control radar logging parameters and save radar data. The developed platform was verified using 24 GHz multiple channel FMCW (Frequency Modulated Continuous Wave) in an environment of stationary and moving targets of chamber room.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.582-587
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• 2004

Ultrasonic sensors are widely used in mobile robot applications to recognize external environments, because they are cheap, easy to use, and robust under varying lighting conditions. However, the recognition of objects using a ultrasonic sensor is not so easy due to its characteristics such as narrow beam width and no reflected signal from a inclined object. As one of the alternatives to resolve these problems, use of multiple sensors has been studied. A sequential driving system needs a long measurement time and does not take advantage of multiple sensors. Simultaneous and pulse coding driving system of ultrasonic sensor array cannot measure short distance as the length of the code becomes long. This problem can be resolved by multi-frequency driving of ultrasonic sensors, which allows multi-sensors to be fired simultaneously and adjacent objects to be distinguished. Accordingly, this paper presents a simultaneous and multi-frequency driving system for an ultrasonic sensor array for object recognition. The proposed system is designed and implemented using a DSP and FPGA. A micro-controller board is made using a DSP, Polaroid 6500 ranging modules are modified for firing the multi-frequency signals, and a 5-channel frequency modulated signal generating board is made using a FPGA. To verify the proposed method, experiments were conducted in an environment with overlapping signals, and the flight distances for each sensor were obtained from filtering of the received overlapping signals and calculation of the time-of-flights.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.154-160
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• 2004

In this paper, implementation of active noise curtains using multiple channel adaptive filters is presented. The same numbers of single channel LMS algorithms as control loudspeakers is used instead of a multi-channel LMS algorithm to reduce the computational burden of adaptive filter algorithms. In general, a multi-channel LMS algorithm is usually used in active noise control system. but this algorithm has much more computational complexity. The single channel control techniques have less amount of DSP calculation, compared to multiple channel control techniques. A stabilizing procedure for adaptive IIR filters is also proposed to improve the stability of recursive LMS algorithms. Both experimental results of two control techniques using TMS320VC33 digital signal processor show the similar noise reduction, but the single channel control techniques are more efficient in practical active noise curtain applications

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.371-374
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• 2004

Induction motors are a critical component of many industrial processes and are frequently integrated in commercially available equipment. Safety, reliability, efficiency, and performance are some of the major concerns of induction motor applications. Preventive maintenance of induction motors has been a topic great interest to industry because of their wide range application of industry. Since the use of mechanical sensors, such as vibration probes, strain gauges, and accelerometers is often impractical, the motor current signature analysis (MACA) techniques have gained murk popularity as diagnostic tool. Fault tolerant control (FTC) strives to make the system stable and retain acceptable performance under the system faults. All present FTC method can be classified into two groups. The first group is based on fault detection and diagnostics (FDD). The second group is independent of FDD and includes methods such as integrity control, reliable stabilization and simultaneous stabilization. This paper presents the fundamental FDD-based FTC methods, which are capable of on-line detection and diagnose of the induction motors. Therefore, our group has developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. This paper presents its architecture. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current, voltage, temperatures, vibration and speed of the motor. The DSPs share information from each sensor or DSP through DPRAM with hardware implemented semaphore. And it communicates the motor status through field bus (CAN, RS485). From the designed system, we get primitive sensors data for the case of normal condition and two abnormal conditions of 3 phase induction motor control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using CAN protocol.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.89-95
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• 2009

Tracking the Maximum Power Point(MPP) of a photovoltaic(PV) array is usually an essential part of a PV system. The problem considered by MPPT techniques is to find the voltage $V_{MPP}$ or current $I_{MPP}$ at which a PV array should operate to generate the maximum power output PMPP under a given temperature and irradiance. The MPPT control methods, such as the perturb and observe method and the incremental conductance method require microprocessor or DSP to determine if the duty cycle should be increased or not. This paper proposes a simple and fast analog MPPT method. The proposed control scheme will track the MPP very fast and its hardware implementation is so simple, compared with the conventional techniques. The new algorithm has successfully tracked the MPP, even in case of rapidly changing atmospheric conditions, and Has higher efficiency than ordinary algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.30-35
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• 2009

In this paper, we propose the flexible design architecture for a continuous packet connectivity (CPC) Protocol among additional features of 3GPP HSPA+. In order to meet a practical intellectual property (IP) reuse and the developing time reduction design goals, we utterly take a CPC protocol into account to be realized by reusing digital signal processor (DSP) IP of the proven high speed packet access (HSPA) platform with the minimum hardware modification and addition. Based on the Teak series DSP, the proposed CPC protocol is divided into discontinuous transmit and receive mode, CPC manager, and interface with the proven HSPA platform. According to the regularized verification flow for wireless cellular communication applications, the proposed CPC protocol has been verified in various test scenarios.