• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.4
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• pp.267-273
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• 2007

This paper presents the implementation of an educational kit for intelligent system control education. Neural network control algorithms are presented and control hardware is embedded to control the inverted pendulum system. The RBF network and the MLP network are implemented and embedded on the DSP 2812 chip and other necessary functions are embedded on an FPGA chip. Experimental studies are conducted to compare performances of two neural control methods. The intelligent control educational kit(ICEK) is implemented with the inverted pendulum system whose movements of the cart is limited by space. Experimental results show that the neural controllers can manage to control both the angle and the position of the inverted pendulum systems within a limited distance. Performances of the RCT and the FEL control method are compared as well.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.376-379
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• 1999

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.103-108
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• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.405-410
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• 2006

Future GNSS signal using BOC modulation brings the advantages of positioning accuracy and multipath rejection. However, the BOC signal has an ambiguous autocorrelation function that complicates the process of acquisition. Three techniques that solve the ambiguous problem are BPSK-like, Sub Carrier Phase Cancellation, and Bump Jumping. In this paper, these methods are implemented by means of a DSP/FPGA board. Moreover, an experiment is conducted to examine and compare the performance of these techniques.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1381-1388
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• 2014

This paper is proposed a wavelet-based the order statistics MAD(Median Absolute Deviation) method of SAR(Synthetic Aperture Radar) image for image enhancement. also The method of compared and defined the threshold the wavelet coefficients using MAD of the wavelet coefficients of the detail subbands was proposed to effectively image enhancement. In order to complement the disadvantage, the threshold of the proposed method sets up the image statistic and excludes the distortion. The hardware design is used FPGA of Xilinx and DSP system for the image enhancement and compressed encoding of the proposed algorithm. Therefore the proposed method is totally verified by comparing with the several other images.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2295-2297
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• 2004

원자로의 제어봉 구동장치에 공급되는 전력을 제어하는 전력함 전력제어기는 DSP를 이용하여 디지털 시스템으로 설계하였다. 전력제어기는 Master/Slave 형태로 이중화되어 신뢰성이 향상시켰고 전력제어기의 CPU 보드에는 제어용과 통신용 두 개의 DSP를 사용하여 전력제어기의 주 기능인 제어/감시와 통신 기능을 분리하여 담당시켰다. 전력제어기에 요구되는 이러한 기능들을 효과적으로 수행하도록 CPU 보드에 디지털 논리구현 장치인 FPGA를 설치하여 메모리 주소 및 각 부품의 칩 선택 신호를 생성, 이중화 전력제어기 상호간 신호 수수, 각종 고장 검출 및 점호각 신호 발생 등의 역할을 하도록 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• International Journal of Automotive Technology
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• v.6 no.2
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• pp.171-181
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• 2005

The purpose of this paper is two-fold: 1) A novel algorithm in order to extract lane-related information from road images is presented; 2) Design specifications of an image processing onboard unit capable of extracting lane­related information in real-time is also presented. Obtaining precise information from road images requires many features due to the effects of noise that eventually leads to long processing time. By exploiting a FPGA and DSP, we solve the problem of real-time processing. Due to the fact that image processing of road images relies largely on edge features, the FPGA is adopted in the hardware design. The schematic configuration of the FPGA is optimized in order to perform 3 $\times$ 3 Sobel edge extraction. The DSP carries out high-level image processing of recognition, decision, estimation, etc. The proposed algorithm uses edge features to define an Edge Distribution Function (EDF), which is a histogram of edge magnitude with respect to the edge orientation angle. The EDF enables the edge-related information and lane-related to be connected. The performance of the proposed system is verified through the extraction of lane-related information. The experimental results show the robustness of the proposed algorithm and a processing speed of more than 25 frames per second, which is considered quite successful.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.7
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• pp.498-506
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• 2003

A computer vision system applied to an intelligent safety vehicle has been required to be worked on a small sized real time special purposed hardware not on a general purposed computer. In addition, the system should have a high reliability even under the adverse road traffic environment. This paper presents a design and an implementation of an onboard hardware system taking into account for high speed image processing to analyze a road traffic scene. The system is mainly composed of two parts: an early processing module of FPGA and a postprocessing module of DSP. The early processing module is designed to extract several image primitives such as the intensity of a gray level image and edge attributes in a real-time Especially, the module is optimized for the Sobel edge operation. The postprocessing module of DSP utilizes the image features from the early processing module for making image understanding or image analysis of a road traffic scene. The performance of the proposed system is evaluated by an experiment of a lane-related information extraction. The experiment shows the successful results of image processing speed of twenty-five frames of 320$\times$240 pixels per second.