• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.996-1002
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• 2000

Ferroelectric (Ba, Sr) TiO$_3$(BST) thin films have attracted much attention for use in new capacitor materials of dynamic random access memories (DRAMs). In order to apply BST to the DRAMs, the etching process for BST thin film with high etch rate and vertical profile must be developed. However, the former studies have the problem of low etch rate. In this study, in order to increase the etch rate, BST thin films were etched with a magnetically enhanced inductively coupled plasma(MEICP) that have much higher plasma density than RIE (reactive ion etching) and ICP (inductively coupled plasma). Experiment was done by varying the etching parameters such as CF$_4$/(CF$_4$+Ar) gas mixing ratio, rf power, dc bias voltage and chamber pressure. The maximum etch rate of the BST films was 170nm/min under CF$_4$/CF$_4$+Ar) of 0.1, 600 W/-350 V and 5 mTorr. The selectivities of BST to Pt and PR were 0.6 and 0.7, respectively. Chemical reaction and residue of the etched surface were investigated with X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.78-85
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• 1995

We fabricated the Pb$_{1-0.28{\alpha}}La_{0.28}TiO_{3}$ (PLT(28)) thin film successfully by using the sol-gel method and characterized it to evaluate its potential for being utilized as the capacitor dielectrics of ULSI DRAMs. In our sol-gel process, the acetates were used as the starting materials. Through the TGA-DTA analysis, we established the excellent fabrication conditions of the sol-gel method for the PLT(28) thin film. We obtained the dense and crack-free PLT(28) thin film of 100% perovskite phase by drying at 350$^{\circ}C$ after each coating and final annealing at 650$^{\circ}C$. Its electrical properties were measured from the planar capacitors fabricated on the Pt/Ti/SiO$_{2}$/Si substrate. By the P-E hysteresis measurement, its paraelectric phase was identified and its dielectric constant and leakage current density were measured as 936 and 1.1${\mu}A/cm^{2}$, respectively. Those electrical values indicate that the PLT(28) thin film is the most successful candidate for the capacitor dielectrics of ULSI DRAMs at the present.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.4
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• pp.809-815
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• 2000

The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.59-70
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• 1993

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.15-24
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• 2000

The dielectric relaxation of high-dielectric capacitors could be understood as a dynamic property of the capacitor in the time domain, which is regarded as a primarily important charge loss mechanism during the refresh time of DRAMs. Therefore, the equivalent circuit of the dielectric relaxation of the high-dielectric capacitor is essentially required to investigate its effects on DRAM. Nevertheless, There is not any theoretical method which is generally applied to realize the equivalent circuit of the dielectric relaxation. Recently, we have developed a novel procedure for the circuit modeling of the dielectric relaxation of high-dielectric capacitor utilizing the frequency domain. This procedure is a general method based on theoretical approach. We have also verified the feasibility of this procedure through experimental process. Finally, we successfully investigated the effect of dielectric relaxation on DRAM operation with the obtained equivalent circuit through this new method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.99-100
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• 2009

SGOI 1T-DRAM cells with various Ge mole fractions were fabricated and compared to the SOI 1T-DRAM cell. SGOI 1T-DRAM cells have a higher leakage current than SOI 1T-DRAM cell at subthreshold region. The leakage current due to crystalline defects and interface states at Si/SiGe increased with Ge mole. This phenomenon causes sensing margin and the retention time of SGOI 1T-DRAMs decreased with increase of Ge mole fraction.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.475-479
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• 2000

The box capacitor structure with H5G-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a 0.482f${\mu}{\textrm}{m}$$^2$ for 128Mbit DRAM. An H5G-Si formation technology with seeding method, which employs Si$_2$H$_{6}$ molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled H5G-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.s.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.244.1-244.1
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• 2011

Memristors have been studied for many years due to better scalability than DRAMs and FLASH memories thus they are considered now as a strong candidate for future memories. To describe the electrical behavior of memristors, various memristor models have been developed. Especially, many kinds of window function have been used to express the non-linearity of memristors which are thought to cause different voltage-current relationships in memristors. In this paper, the previous memristor models with different window functions are compared and analyzed. This comparative study can be very useful in not only understanding the diversity in memristor's electrical behaviors but also developing memristor circuits. This work was financially supported by the SRC/ERC program of MOST/KOSEF (R11-2005-048-00000-0). The CAD tools were supported by the IC Design Education Center (IDEC), Korea.